A couple of months ago, I blogged about a new 100GbE backplane project on the horizon that might also be leveraged for a narrower cable solution than the current 100GBASE-CR10 option that requires 10 differential pairs in each direction. At the November IEEE Plenary in Dallas, the first steps were taken as a study group was formed to start examining this problem.
Timing is everything. It takes time to develop solutions. It takes time to develop a standard. It takes time to develop products. It takes time for a market to develop. And it takes time to recognize that all of this is a matter of timing.
So if we follow Mr. Moore’s guidance and look to 2017 for 100GbE servers for the mass x86 market, we might ask “Why start now?” Well, there are a few good reasons. First, it is easy to envision how 10GbE / 40GbE and 100GbE-based front panel capacities will challenge the ability of a backplane to keep up.
Next, while 100GbE blade servers won’t hit the mass market until 2017, backplanes delivered prior to then will be expected to be upgradeable to support 100GbE. The same is true for the top / middle-of -rack architectures being deployed in data centers today as we speak.
10GbE was a push technology and, as we look back at the first decade of the 21st century, we see examples of how the industry tried to push 10GbE technology into the mass volume shipments that GbE has enjoyed. And it almost seems like 10GbE was lost for a time. Development cycles have been spent on 10GBASE-CX4, Backplane Ethernet, 10GBASE-T, SFP+, and active cable solutions. As a result, there is not one dominant solution out there like 1000BASE-T has enjoyed. One can almost see Dr. Evil talking about the gazillions of ports shipped.
But as we look to the next decade, there appears to be more thought being given to the planning of things to make life more logical and productive for everyone. Or is it just wishful thinking on my part?
And before I forget timing, as we talk about 100GbE servers, I have a number of people reminding me that we will need the next speed of Ethernet to support the aggregation needs of networks based on these servers.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.