In my last Dew Point column I lamented the fabless approach to the chip business. Questioning the widely accepted outsourcing model attracted several reader comments. Anyone interested in the topic may be interested to look at those reader comments as they are insightful and a few offer some additional historical perspective. At least there was one comment that can be spun to appear to agree with my commentary: "The semiconductor industry was way more fun back in the 1980s, when dinosaurs like Jerry Sanders still roamed."
Dylan McGrath commented that the fabless model has been an unqualified success. But perhaps I was not quite getting to the heart of the matter as much as other commentators.
Bolaji Ojo wrote a recent piece on the outsourcing craze and where it has left us, warning us to Stop Gorging on China. There's more to the China story than just cheap labor. China's control of rare earth metals moved Toshiba to enter into talks with the Mongolian government to develop new sources for these critical materials.
As for IC production, it also made good business sense to shift to the pure play foundries in Asia, and the foundries in Taiwan got started at just the right time. Dennard's scaling model worked well, and the performance of new generations of CMOS devices was predictable. There was an opportunity to take mature, stable processes near the end of the learning curve and squeeze out any unnecessary costs. Chip companies began to see process technology less as a differentiator and more as a huge expense line. TSMC offered a flexible manufacturing option and continued to grow and invest in more capacity. The pure play foundries started to invest in research and development eventually moving closer to the leading edge of technology. Their growth to prominence took place before physical scaling for device performance was replaced with strain and other materials engineering. By the time gate length scaling was no longer able to keep transistor performance on track, TSMC was an industrial giant able to develop its own new technology strategies and was already emerging onto the forefront of industry research.
Staying competitive in semiconductor manufacturing today requires intensive research efforts into materials that can outperform silicon in planar technology platforms and eventually a replacement for planar devices. Today's contract wafer manufacturer does a lot more than take an existing recipe and apply operational efficiencies to reduce costs. Moving production to Asia, however inevitable it was, meant the loss of re-investment in North America for research and development. Perhaps Globalfoundries will bring some of that production, ecosystem and R&D back to the U.S. The bigger question is probably how long it can keep it there.
Speaking of advanced technology development, the International Electron Devices Meeting is less than a week away. Each year, I like to preview this IEEE conference since it is a leading forum for semiconductor technology. After revisiting the "Real Men" column, I am out of space for a complete rundown of the sessions. I intend to highlight more papers in the days ahead, but for now, let's stick to the theme.
Part of the motivation for writing about the fabless model was the belief that a tighter bond between circuit designers and manufacturing becomes more important with every new node. Whether those functions are engineering teams under the same corporate banner of an IDM or through vendor partnerships, it's a fact. And that was the motivation for IEDM creating a special session in 2007 that invited members of the design community to give their view of process technology development. That session continues this year. The emphasis of the 2010 edition, Session 17 – Confluence of Technology and Design, is "Challenges for Non-Conventional Devices and 3D LSIs."
With the exception of session chair Kazunari Ishimaru of Toshiba, there are no fabless chip companies, foundries, or even IDMs represented. All the authors are from academia. The abstract of one paper does claim collaboration with IBM, however. Thermal-Aware Design of 3D ICs with Inter-Tier Liquid Cooling is from D. Atienza of the Embedded Systems Laboratory at EPFL. As much as we hear about through-silicon via and 3D IC, this research on microfluidic channels for chip cooling will not spawn any consumer products for a very long time. Session 17 may boast the catchiest title of the conference, May the Fourth (Terminal) Be With You - Circuit Design Beyond FinFET, is a paper by H. Koike and co-authors from Japan's National Institute of Advanced Industrial Science and Technology (AIST). But getting down to the annual business of choosing some talks to attend (if you are lucky enough to be attending IEDM), this session boasts one industry guru that I would like to hear from. H.-S. Philip Wong of IBM fame and now at Stanford has contributed Device and Circuit Interactive Design and Optimization Beyond the Conventional Scaling Era.
Finally, I should note that even the IEDM program shows the broad acceptance of the fabless business model. Qualcomm, the poster child of the movement, will be represented by James Clifford, Senior VP and General Manager of Operations at the IEDM Luncheon on Tuesday, December 7.