An engineer scurries to make up time in adding a missing feature to a display generator
Back in the 1980s as a young engineer, I was basking in the glow of a recently completed VME circuit card design (it had been sent out for PWB, or printed wiring board, design/build). But that good feeling didn't last long. I returned to work the following Monday morning, only to be IMMEDIATELY whisked off to a meeting. Apparently, we had been forging ahead so swiftly on our display generator design, that one of the systems engineers had failed to identify a missing feature that now had to be designed into our display generator box: a cursor generator (there had to be two different cursor types as well).
A cursory analysis of two cards that were already in the video circuit (with timing signals already on board) revealed that they were 100% full. In the days before surface-mount components, it was not possible to make up for a shortage of "real estate" on a circuit board by changing a few components to smaller outline versions. Neither the four Image Memory (IM) planes nor the Raster Video Generator (RVG) had sufficient room to add this function. A new circuit card in the box would be necessary. Luckily, the RVG card and the backplane were designed to accommodate up to 6 IM planes, so we were able to plug the dual cursor card (DCC, as it was now known) into a spare IM plane slot.
The systems design completed, I now could proceed to design the circuit card. Imagine my consternation when I discovered that it was due to PWB design in one month! What to do? I guess I did what every other young engineer would do – I "buckled down" and got to work.
I allocated two weeks to capture the schematic, one week to work the bugs out of the design placement, and one for timing analysis and simulation. The old VALID Logic Systems TM schematic capture/timing verifier/simulator was not very intuitive. Once you captured the schematic, you had to "compile" it. This took the visible design and converted it to connections. Next, you would run "package," which would replace the ICs included in the design with their timing and simulation models. This would include setting timing constraints on key signal routes in order to ensure that the high frequency video signals would be routed on the shortest paths.
To an experienced designer, schematic capture was mostly "monkey work," so I chose to compress that schedule as much as possible (simulation and timing verification would require my full attention, so I wanted to make sure I was as "fresh" as possible for this part of the design phase).
What ensued at this point was the following schedule: drag into work at 9AM, work through lunch until 6 PM, go home and eat dinner, return to work at 8PM and work until 2AM. I was obviously stressed out by this. On one occasion, I actually woke up in the middle of the night, moving my right hand back and forth in the air in front of me, as if I were drawing a schematic in my sleep. (I am still smiling about that almost 20 years later). I continued with this schedule for the better part of a month, as there had been issues with the timing models developed by the chief engineer. This board heavily relied on 7400 "F –series" TTL logic, as the data was at video data rates – fast for the time (mid-1980s).
Finally, the design was finished and I could create the TelesisTM –compatible netlist for the PWB design system. It was a long haul, but it was now done. Surprisingly, there was only one error in the design: when the cursor was displayed, the rightmost column of pixels was clipped off. As many times as we had done this calculation, we ended up putting one too many register stages in the video path, shifting the image one pixel to the right.
My solution was simple: just make an "asynchronous register" (???). Well, actually I replaced a 74F174 4 bit register with a 74F10 AND gate. Basically, an AND gate was substituted for each "D" flip flop section of the F174 that was replaced. One input of the AND gate was pulled up and the other passed the signal through.
There was just enough Setup Time in the RVG card input to allow for the F10’s propagation delay and there was already a pullup wired to the chip. I then wired up a special chip socket to adapt the F10’s pinout to the F174’s and I was done.
I have to admit it looked a little funny, but we were able to make it through system integration with that board while awaiting the new PWB. My boss was impressed with my "Rube Goldberg" solution to the problem, especially because it worked.
Author Dwight Bues is a Georgia Tech Computer Engineer with 27 years experience in Computer Hardware, Software, and Systems and Interface Design