To feed the need for speed by telecommunications applications, the signal integrity performance of the interconnects has had to constantly improve. But there is a sea change occurring in the FPGA world that is changing this trend.
Starting with the transatlantic telegraph cable, laid in 1866, telecommunications applications have always been the driver for the highest data rate systems. To feed this need for speed, the signal integrity performance of the interconnects has had to constantly improve. But there is a sea change occurring in the FPGA world that is changing this trend.
"If you look at the last few generations of systems, the bit rate has been increasing, from 3 Gbps to 6 to 10 and soon to 14 and then on to 28 Gbps, but the interconnect has stayed largely the same," Dr. Mike Peng Li, principal architect and distinguished engineer with Altera said in an interview recently.
In the last few generations of high speed serial links, what has overcome the limitations in the interconnects' performance and enabled the constant march to higher data rate has been the silicon. This trend is continuing in the next generation of FPGAs recently announced by Altera.
"We see internet backbone applications driving the need for speed," Salman Jiva, product marketing manger at Altera said recently. To implement 100 Gbps Ethernet optical modules, line cards typically multiplex 10 lanes, each running at 10 Gbps. But, Jiva says, this will evolve to 4 lanes at 25 Gbps followed by 10 or more lanes at 25 Gbps.
While Altera has been shipping FPGAs operating at 10 Gbps since 2008, they recently announced transceivers operating at up to 28 Gbps per channel. This means much of the multiplexing can be done in the FPGA and fewer components needed on the line cards to feed the data hungry optical modules.
But, it's more than just using the 28-nm high performance process technology from TMSC that enables successful 28 Gbps transceivers, Li, hastens to add.
In a recent interview, Li and Jiva mentioned four important new features coming to market in the latest generation of FPGAs, such as the Stratix V, that help to overcome the interconnect barrier posed by conventional circuit boards, and balance the cost-performance-power tradeoffs.
Data reliability is measured by the bit error rate. A typical product spec is to have no errors in the received data during the life of the product. If the lifetime is 5 years, and the data rate is 28 Gbps, the bit error rate (BER) must be less than 10-18.