Poor schedule predictability of IC development projects is often blamed on unforeseeable events, but this picture is incomplete and inaccurate.
Poor schedule predictability of IC development projects is the Achilles heel of semiconductor companies. It manifests itself as high schedule slip and is among the most important R&D metrics, measuring how well project schedules reflect reality. Most don't.
Companies traditionally view schedule slip not as a result of faulty project plans, but rather as a consequence of unforeseeable perturbations occurring during the development process. The picture is incomplete and inaccurate. Slip must also be viewed through the project planning lens, because many events labeled as unforeseeable can be fully contemplated in the project plan with proper modeling. The payoff is big—reliable plans, which is the path to profitability.
Predictability and schedule slip are two sides of the same coin. Schedule predictability measures schedule overrun by comparing a project's original planned duration to its actual duration, expressing the difference as a percentage of the original. The original planned schedule is the first one formally defined and officially disseminated.
What qualifies as low versus high slip in the semiconductor industry? Low is 10 percent or less. High is more than 25 percent.
Poor schedule predictability is an insidious problem that eats away at a company's competitiveness, especially when it becomes fully baked into the organization's culture as a tolerated practice. At that point, it's just a matter of time before the company or business line disintegrates. Today many semiconductor organizations are taking action to vanquish slip. Those ignoring it do so at their peril. I doubt they'll be around five years from now.
Excuses abound during post mortem assessments of projects that slip schedule. Naturally, the usual culprits are speciously defended as wholly unforeseeable. They include spec changes, EDA tool and library problems, IP and software delays, personnel issues, etc. But what project doesn't encounter some or perhaps all of these and more? It's disingenuous to expect that any particular project will escape the stochastic nature of chip development, so therefore it must be built into the plan—without the use of schedule buffers at every turn.
I reject the notion that IC projects are predictably unpredictable. I can point to myriad organizations that have excellent predictability. These groups deploy best practices and tools that use facts and data to ensure project plans fully contemplate the stochastic nature of IC development and "unforeseeable" events.
Ronald Collett is president and CEO of Numetrics Management Systems Inc.