I love my Google automated searches that ferret out all the latest information on the web that may be of interest to me without having to do the searches manually. The other day, for example, I found out that AccelChip, a company acquired by Xilinx back in 2006, had in effect been reborn.
AccelChip took models described in MATLAB (from The Mathworks) and – coupled with a library of IP – transformed them into RTL suitable to be placed on an FPGA. Now, fast forward five years and I find a new company called BinaChip, made up of many of the same founders or key players that describe themselves in this manner:
ESLerate is the industry’s only high-level synthesis solution that provides a path for translating binary code for general-purpose embedded processors into powerful, tightly-coupled RTL hardware accelerators for SoC FPGA architectures. Its powerful engine improves performance, area, and power, while minimizing design costs by reducing development and debugging time from months into hours.
So while many other companies have attempted to create tightly coupled accelerators from source code (such as Poseidon Designs with which I was once associated), and companies such as Critical Blue
take binary code intended for one processor and map it into multicore architectures, this may be the first attempt to go from binary software code into hardware.
Actually, this may map into the type of company that I was talking about in my last blog titled The ESL Dilemma
that would enable software engineers to effectively use an FPGA accelerator build into a PC or other consumer device. Now I have not played with their tool in any way, neither do I know what their business model is, so I may be all wrong about them. So I was excited and started to dig further and then found this:
The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of tools while the tool does the RTL implementation.
Now hang on here! Now they say that this is for hardware designers. Dang. I was hopeful. Then they say:
The algorithm is generally modeled [in] one or more high-level languages such as C, C++, SystemC, or Matlab.
What happened to that binary code? Now this is beginning to sound like all of the other high-level synthesis companies out there except they accept both C based languages like Mentor, Cadence and Forte, and MATLAB like Synopsys through its acquisition of Synfora, which also used to target FPGAs. Digging still further I find that they do also accept binary code so that existing embedded applications can use their software. So it seems as if they are trying to attack both markets, although that may be leading to somewhat confused messaging.
Now from experience when you are attempting to create accelerators, one of the critical functions is getting the data where it needs to be at the right time and this can often be a performance killer. The other problem is tying things back together when an RTOS is involved. Have they solved these problems? No clues on the website, but I will find out.
They plan to exhibit at both ESC and DAC, so this will surely be one company to add to the “must see” list.
Do we really need another high-level synthesis company? Well at least this is one that is targeting FPGAs almost exclusively so that is a bonus, and they are targeting existing embedded software as well as description written explicitly for hardware, but I will need a lot more information about them, their technology and their business model before I can say if they really are something new and noteworthy, or just another company trying to pile onto an already overcrowded field. I had predicted that we would see more consolidation this year, but had not expected new entrants.
Brian Bailey – keeping you covered