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Another high-level synthesis company targeting FPGAs

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KarlS
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re: Another high-level synthesis company targeting FPGAs
KarlS   1/29/2011 7:22:37 PM
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Hi Dr. DSP This approach requires that binary be generated then transformed into wires and registers in a unique physical pattern with all the placement/routing/timing analysis complications. Why not a design that runs at the source code level so that a few designs with different capacities can be used to cover a range of applications? Just reload the memories to change the function but not the physical layout. That is part of the mpu advantage but debug requires knowing all the processes of the compiler and the cpu instruction set details. Of course the fact that one may have to use C++ rather than C to access the MMIO registers doesn't make anything simpler.

KarlS
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re: Another high-level synthesis company targeting FPGAs
KarlS   1/29/2011 5:11:59 PM
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The GCC compiler generates what is called RTL which is then back end compiled to specific cpu instruction sets. I may have the wrong acronym but Wikipedia has a description. Basically two registers are manipulated by an operator and the result put in to a register. Compiler optimization is included, so it sounds like they are putting the registers and data flow operators on the FPGA, bypassing the C to HDL step. Like all the pie in the sky schemes, we will have to wait awhile to see how well it works.

DrFPGA
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re: Another high-level synthesis company targeting FPGAs
DrFPGA   1/26/2011 7:38:12 PM
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There is clearly a need to move us up the design ladder to something above pushing signals into registers. I hope these guys can do it- the approach of taking processor code might be a good one...

Max The Magnificent
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re: Another high-level synthesis company targeting FPGAs
Max The Magnificent   1/25/2011 3:57:21 PM
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Very interesting Brian -- I used to know some of the folks at AccelChip -- I look forward to discovering more about this BinaChip reincarnation -- Max

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