Now, MATLAB-Simulink, RocketDrive, and RocketVision can be used in conjunction with each other to significantly speed the entire design-debug-verification flow.
I just know that I’m going to get groaning and moaning emails from the folks at the MathWorks about my saying that you can “Turbo-Boost” MATLAB-Simulink, but as far as I’m concerned this is the ultimate effect as seen by the designers in the trenches, so take me outside and spank me now!
As we all know, compared to even a few years ago, todays FPGAs offer incredible increases in performance and capacity, and they are now key components in an ever-increasing range of high-end applications in multiple markets, including aerospace, automotive, broadcast, consumer, industrial, scientific, medical, and wired and wireless communications.
An increasingly important element of almost every modern design is that of digital signal processing (DSP). Having high-performance multi-million-gate equivalent FPGAs provides engineers with the potential to create incredibly sophisticated products that perform vast amounts of computationally-intensive DSP tasks … but this also mandates state-of-the art tools that can bridge the design, debug, and verification gaps.
On the design side of things, MATLAB-Simulink from the folks at the MathWorks (www.mathworks.com) provides a way to capture and evaluate alternative design scenarios at a high-level of abstraction using extremely powerful stimulus generation and analysis and plotting capabilities. Meanwhile, RocketDrive and RocketVision from the guys and gals at GateRocket (www.gaterocket.com) dramatically accelerate the debugging and verification of the design in a physical FPGA. Now, MATLAB-Simulink, RocketDrive, and RocketVision can be used in conjunction with each other to significantly speed the entire design-debug-verification flow.
Let’s briefly remind ourselves as to the way the various portions of the flow work in isolation, and then we’ll see how they can be used together to speed the FPGA development process. Both Altera and Xilinx have worked with The MathWorks to create libraries of DSP functions called Blocksets. Algorithm developers can use Simulink’s graphical interface to capture block-level schematics based on these DSP blocks. They can also use Simulink’s own rich stimulus generators to create testbenches and then use its sophisticated analysis and plotting capabilities to evaluate various design scenarios.
At some stage, the designers will be ready to proceed to the RTL level of abstraction. Altera’s DSP Builder can take an Altera Blockset-based design in Simulink and generate an RTL equivalent. Similarly, System Generator for DSP from Xilinx can perform the same task with a Xilinx Blockset-based design in Simulink.
Now, here’s the clever part, because the chaps and chappesses at the MathWorks have created a tool called EDA Simulator Link. This allows Simulink to work in conjunction with any industry-standard software simulator. The advantage of this scenario is that even after the design has been translated into RTL, designers can still use the original stimulus generators in Simulink to drive the design and they can still use the rich analysis and plotting features in Simulink to display and analyze the results. The only downside is that the combination of Simulink, EDA Simulator Link, and the software simulator runs at around a third of the speed of the original Blockset-based simulation in Simulink.
RocketDrive and RocketVision
Now let’s turn our attention to RocketDrive and RocketVision. One problem with FPGAs is that the results seen at the RTL level sometimes don’t match the results seen from the gate-level representation of the design after it’s been loaded into the FPGA. The GateRocket RocketDrive was uniquely developed to solve debugging problems with the traditional FPGA design process by bridging the gap between the RTL and the FPGA. A traditional deployment is as illustrated below:
As each new block is verified at the RTL level in the context of your full-chip design, its synthesized/gate-level equivalent (generated using any industry-standard synthesis tool) can be moved over into the physical FPGA in the RocketDrive. Meanwhile, RocketVision allows you to gain access to any internal signals to see what’s going on inside the FPGA.
As soon as a problem manifests itself, the verification run can be repeated with the RTL version of the suspect block resident in the software simulation world running in parallel with the gate-level version realized in the physical FPGA. By means of RocketVision, the signals from the peripheries of these blocks (along with any designated signals internal to the blocks) can be compared "on-the-fly."
Using this technology – combining conventional software simulation with physical hardware and an appropriate debugging environment – it is possible to very quickly detect, isolate, identify, and resolve bugs, irrespective of where they originated in the FPGA design flow.
And one very important point to note here is that the design in the FPGA runs at hardware speed, which is much, MUCH faster than the RTL equivalent running in a software simulator.
MATLAB-Simulink + RocketDrive + RocketVision
Now this is where things start to become very exciting. As we’ve already seen, EDA Simulator Link from the MathWorks allows Simulink to work with any industry-standard software simulator. Meanwhile, the RocketDrive and RocketVision also work with any industry-standard software simulator. So when everything is brought together, we can enjoy the advantages provided by all of these tools.
The best way to illustrate this is by means of a demonstration. By some strange quirk of fate, the folks at GateRocket have a video of just such a demonstration (Click Here
to see the demonstration). As you’ll see, they commence with a Simulink-based simulation of a DSP function using the Xilinx DSP Blockset. This simulation takes 133 seconds to run. (Actually, it should be noted that these FPGA Blockset-based simulations in Simulink run slower than simulations using Simulink’s native software-based blocks. However, this is somewhat irrelevant, because the whole premise of what we’re talking about her is based on the use of the FPGA vendors’ Blocksets.)
Next, the guys and gurls at GateRocket use the Xilinx System Generator for DSP to generate the equivalent RTL. Then they employ EDA Simulator Link to perform a co-simulation of the testbenches in Simulink with the RTL in the software simulator. This simulation takes 435 seconds (three times as long) to run.
Finally the chaps and chappesses at GateRocket use the combination of Simulink (for the stimulus and display) with EDA Simulator Link, an industry-standard software simulator, and the RocketDrive and RocketVision. The resulting simulation runs in only 10 seconds, which is 13X faster than the Simulink-only run and 43X faster than the Simulink plus software simulator run.
Personally, I think this is rather exciting. What we have here is a new way to tie existing design, analysis, debug, and verification technologies together so as to reap the advantages of each of the tools. And this is only one possible scenario... now I’m looking forward to seeing what the folks at GateRocket come up with next...