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From timing to power: the shift in modeling standards

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old account Frank Eory
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re: From timing to power: the shift in modeling standards
old account Frank Eory   2/4/2011 10:33:38 PM
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Attempting to model power at the system level is going to be quite a daunting task -- but a necessary one. Power modeling at the gate level is now fairly mature, but we still can't say with any accuracy how much power the chip dissipates -- because the answer is always "it depends on the application." In other words, somewhere between the deep sleep mode dissipation and the everything-running-full-blast dissipation.

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