There's been a shift in what's needed in modeling standards for IC design. The focus has moved from timing to power consumption. Timing modeling, which dominated much of the effort from the early to mid 00's, has sorted itself out. The Liberty format (.lib) has been successfully extended for demanding nanometer timing accuracy by customers and EDA suppliers via collaboration in the Liberty Technical Advisory Board (LTAB). Other groups such as OMC that had sprung up to tackle timing modeling, among other things, have completed their missions and provided direction to the LTAB so that Liberty (.lib) consolidates all the market needs.
Power management of ICs is now the growing challenge, as power modeling and optimization has replaced timing as a critical need for standard modeling during the past couple of years.
Power consumption has to be modeled at both the gate level and the system level. A lot of good work has gone into power modeling at the gate level in Liberty, and this work is ongoing. Several years ago, the LTAB ramped up its efforts in the area of power modeling, in conjunction with the rise of UPF and CPF power formats. Both the IEEE 1801 Low Power Working Group and the Si2 Low Power Coalition (LPC) have been guiding critical extensions to Liberty with respect to gate-level and macro-level power and implementation modeling. The LTAB accepts input from all sources – one doesn't have to be a member to contribute.
This cooperation with IEEE 1801 and LPC is a good example of the First Commandment for Effective Standards: Cooperate on Standards, Compete on Products. The concept is that it's most effective and efficient for companies to cooperate on creating standards. The corollary is that, just as for companies, it's better for standards organizations to cooperate. IEEE 1801 and LPC contributing to the LTAB is the model of cooperation among standards organizations that we can always use more of.
What's coming next for power modeling? The challenges are moving into the system-level space – ESL if you like. As in moving from transistor-level to gate-level modeling, moving from gate-level to system-level means new and/or enhanced standards are needed. Taking power modeling up a level of abstraction, to the transaction-level, will require a lot of system-level expertise that needs to come, not from the gate-level world, but from another space – the system-level space. Power-modeling efforts from the system-level experts will be essential to produce effective standards. The system-level guys will certainly need to play a substantial role.
Just where are the system-level guys? In OSCI, of course. The Open SystemC Initiative has been the center point for system-level modeling since 1999. It only makes sense for system-level power-modeling standards to come from OSCI. In the same spirit as the LPC cooperates with the LTAB for gate-level power modeling, it will be great to have IEEE 1801 and LPC contribute valuable ideas to OSCI as they generate new system-level modeling needs.
Attempting to model power at the system level is going to be quite a daunting task -- but a necessary one. Power modeling at the gate level is now fairly mature, but we still can't say with any accuracy how much power the chip dissipates -- because the answer is always "it depends on the application." In other words, somewhere between the deep sleep mode dissipation and the everything-running-full-blast dissipation.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.