In the shadow of the recent Sale of AutoESL to Xilinx, I was chatting with Brian Durwood, who is one of the co-founders of Impulse Accelerated Technologies (www.impulsec.com). I remember when they just started out and were desperate for attention, but times have moved on and Brian tell me that Impulse now has over 400 customers, including NASA, JPL, Lockheed, Northrop, DoD, Toyota, Honda, Wall Street trading banks, Toshiba, Fujitsu, Philips, Hitachi, Boeing, MIT, and Harvard (phew!).
At the same time, the past few years have seen a number of other high-level synthesis tools exit the scene. For example, Agility (Handel-C), Mitrion (Mitrion-C), and Synfora have either been acquired by other companies or have simply faded away.
Impulse began in 2002 as the descendent of Los Alamos National Laboratories research. Brian attributes Impulse’s market survival to focusing on FPGAs as the end product, vs. using them as a stepping stone to ASICs. Impulse serves software algorithm developers accelerating their applications with known good IP, board interfaces, and an optimizing compiler. Brian also attributes Impulse’s survival to being flexible and expanding to include services that ensure first-time client success. It also doesn’t hurt that the Impulse team succeeded twice before in this market; in the 80’s as part of the ABEL team and in the 90’s with PeakVHDL and PeakFPGA.
Impulse’s current focus on expanding into international markets recently won them a China Electronic News award for their tool category. As Brian told me: “When we first launched HDL products for programmable logic in the 80’s and 90’s, the expectation was 1/2 US, 1/4 Western Europe and 1/4 Japan/Pac rim. Things have changed. We are seeing very good IP come out of what used to be the Eastern Bloc countries, and we have seen China emerge as the fastest-growing area for high-level engineering tools. We continue to be impressed with how engineering organizations in China are embracing the most cutting edge techniques.”
Impulse originated supporting system-on-chip FPGAs with processor cores. It grew to support full computing systems that use FPGAs as coprocessors, adding platform support libraries to enable C programmers to partition applications between C code running on a processor and C code running directly as hardware in the FPGA. According to Brian, there are also Impulse users who are experienced FPGA users who use Impulse tools for fast prototyping of FPGA hardware, without using embedded processors.
The Impulse folk are also enthusiastic supporters of FPGA board vendors, FPGA, and processor (AMD, Intel, embedded) interfaces. Impulse supports a wide range of platforms, all the way from $50 boards to $50,000 accelerated computing systems. Impulse provides I/O interface IP and engineering support for any FPGA accelerated board or system vendor who wants to provide their base with the ability to program I/O, memory and other hardware from C.
The last piece of the rapid spread of Impulse-based uP/FPGA/DSP co-development is their adherence to open architectures and tools that are already widely accepted in the industry. Where some of the now-departed tool vendors created non-standard languages by introducing new keywords, hardware-specific tools, or semantics to the C language, Impulse remained pure ANSI C-compilable in Visual Studio at all times. Impulse also remained open, supporting 60 different FPGA platforms, working with Visual Studio, ModelSim, and all synthesis tools. Impulse also endorsed Open CL and supports academic research such as Innovate North America and Novo-G.
As Brian says: “We view the biggest challenge as getting the message to software developers as to how FPGAs can off-load microprocessors. We anticipate that 10 Gb Ethernet and the resulting increase in video, data, and signal traffic will increase engineer team sampling of FPGAs for hardware acceleration.”
Well all I can say is that I'm delighted things are going so well, and I look forward to hearing more good news like this in the future.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.