I just heard from the folks at Mentor about a free whitepaper that describes how you can create rad-tolerant FPGA designs.
As the guys and gals at Mentor say: "FPGA designers of aerospace and high reliability applications have long been aware of radiation effects on their devices and various techniques to mitigate them. Approaches include the use of rad-tolerant silicon, device- or board-level triplication, or HDL-level mitigation. This white paper takes a high-level view at traditional mitigation strategies, their impact on project cost, risk, and schedule, and a new synthesis-based methodology that offers an easier way to rad-tolerant design."
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