18th Electronic Design Process Symposium is a good venue for discussing the need for 3D ICs standardization.
I'm hearing more and more talk about the need for standards and interoperability in 3D. We mean 3D ICs—stacking chips in a single package—not to be confused with 3D entertainment, which also is looking at creating standards, such as those for 3D glasses.
And more and more action is being taken. Several standards organizations have formed groups to study and/or develop standards for 3D ICs. These include: JEDEC, SEMI, SEMATECH, SIA, SRC, IEEE-SA, IEEE-ISTO, GSA, and Si2. It's not surprising for a new technology to receive a lot of attention from the standards arena. There are technological and business challenges to overcome that can be helped by the introduction of appropriate standards. As the working groups sort out what's needed, who will do what, where competition and cooperation should exist, and which standards will be adopted over others, there could be (OK, there likely will be) the usual turbulence that accompanies all standardization journeys.
The topic of 3D IC standards will be one of the discussions that will happen at the 18th Electronic Design Process Symposium (EDPS). The April 7 to 8, 2011 symposium will be sponsored by three of IEEE's subgroups: Computer Society of Silicon Valley, Council on Electronic Design Automation, and Design Automation Technical Committee.
I've attended EDPS in the past and found it to be especially interesting because of its small, intimate nature. Presenters and attendees are there because they are passionate about their topics. If you're interested in 3D ICs, you might find value in spending a day in Monterey, CA discussing your views and asking questions of other participants.