A few weeks ago, I reviewed the new book from Synopsys about FPGA-based prototyping (Click Here to see that review). In response, Cadence has issued a whitepaper titled ASIC prototyping simplified that talks about their views on the use of FPGAs for verification (Click Here to see the whitepaper).
Now one of the first rules of selling has to be “Sell what you’ve got,” and that is certainly the case with both of these vendors. It makes for an interesting comparison. Cadence does not have an off-the-shelf prototyping solution, while Synopsys does. Cadence has some tools that enable prototype boards to be designed and help with design partitioning, Synopsys has a set of tools that are optimized for FPGA compilation, partitioning, and debug. In my opinion, neither of them is the complete set.
For a direct comparison, we can look at this Cadence whitepaper and Chapter 5 of the Synopsys book. We should also throw in Appendix B of the Synopsys book (Economics of Making Prototype Boards), which provides their cost comparison between build your own and the use of a standard prototyping system.
Cadence postulates that ready-made FPGA prototyping systems are not ideal because of costs, limitations, and performance. They are bold enough to make the statement “Off-the-shelf boards provide an expensive, partial solution that doesn’t enable you to prototype your design and test it fully.” We shall see how well they back up their claims. Synopsys on the other hand says “We tried to avoid making any value judgments between these two approaches because in any given situation one or the other may be most appropriate.” While I will also try and avoid value judgments, I think the Synopsys statement rings true.
Apple 1 Prototype from the C/PMuseum
The Cadence solution is based around their Allegro FPGA System Planner tool suite. The first thing I notice is that many of the statements in the Cadence paper appear to be a lot more loosely defined than for Synopsys and that Cadence appears to have many tools missing, such as software to put on-chip debug logic in place, instead relying on the capabilities provided by the FPGA manufacturers.
The Cadence paper reads like a step by step tutorial on the use of the board layout tool, and never actually backs up any of their claims, which is a shame. The one assertion that they make in the conclusion is that their tool is better than trying to create your own prototype board using a regular PCB design package. Many off-the-shelf prototyping systems are not as rigid as this paper would have you believe and often have many modules that can easily be plugged in to increase certain types of capabilities. The Synopsys software, which supports both their own HAPS platform and other board providers, would appear to have more built in support for techniques such as pin multiplexing and the use of high-speed I/O between the FPGAs.
Appendix B of the Synopsys book looks at both the direct and indirect costs associated with a prototyping decision. On the direct costs side they include personnel, equipment and expertise, materials and components, yield and wastage, support and documentation. For indirect costs they list time, risk and opportunity. I think it is clear that for most companies, each of these will be different. Some companies may have no high-speed board expertise, while others may want large quantities of the prototype. The biggest difference between these two approaches is going to be costs of development on the one hand versus cost of finished materials on the other.
Synopsys estimates that for a typical 4-FPGA board, the layout costs are $40,000 for the necessary engineer, and total engineering costs are somewhere in the neighborhood of $60,000. They come up with a project duration as being a minimum of 15 weeks. Cadence claims that they can halve that cost. Then there are the material costs. It seems logical to me that you will always pay more for the finished product being purchased from someone than you could do it for yourself. They have to make a profit. There may be other factors at play if you already manufacture other board based products. If that is the case you may be able to get components cheaper than, in this case Synopsys, but in other cases it may be the other way around.
For the indirect costs, this is basically a matter of whether the prototype was properly planned, or you need it right now because something is going wrong. If you planned well in advance, and have taken those costs into account, you are likely to have the boards ready when you need them. You are assuming the risk associated with the design, but then there are also risks that the board supplier may not be able to deliver exactly when you want them.
When you plug the amended figures into the Synopsys spreadsheet, you may come up with a different result based on using the Cadence tool suite. I would still imaging that it will vary between different companies, products and usage scenarios. At the end of the day, prototyping is going to become so important that all of the vendors will need to have complete solutions that include both ready-made and custom board solutions. That puts both Synopsys and Cadence ahead of Mentor which has yet to realize the importance of this space.
Brian Bailey – keeping you covered