This Webinar should be a lot of fun, not the least that yours truly (yes, me, myself, I) will be acting as the host. The live webinar takes place on Thursday 14 July at 11:00 a.m. Pacific Daylight Time (2:00 p.m. Eastern Daylight Time).
You will also be able to access the webinar in On-Demand format after the event, but it would be great to see you at the live “happening” – apart from anything else you can ask questions directly to the presenter and/or myself (I’ll answer the obvious one now … yes, I truly am magnificent [grin]).
A brief overview of the webinar is as follows:
The need for high-reliability and high-availability electronic systems has expanded beyond traditional military and aerospace applications. Today communications infrastructure systems, medical and industrial applications, to name a few, need to ensure highly reliable operation and high availability in the face of radiation-induced errors that could result in a satellite failing to broadcast, a telecom router shutting down or an automobile failing to respond to a command, to name a few examples.
In this 1-hour webinar, technical experts from Synopsys will address some of the most significant elements of high-reliability design, including how to effectively implement safety-critical FPGA using logic synthesis.
If you are involved in communications, medical, military, aerospace or other high reliability designs, you won't want to miss this informative webinar.
Click Here to see a full description and to register.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.