Well, this was a shock and no mistake. To say I am unhappy about this doesn't start to cover my feelings...
Have you seen Brain Bailey’s blog Another one Bites the Dust – GateRocket. Well, this was a shock and no mistake. To say I am unhappy about this doesn’t start to cover my feelings…
It’s no secret that I was a big fan of GateRocket’s technology – specifically the RocketDrive hardware and the RocketVision software. In fact I penned a few columns about the little scamps; for example:
- Click Here to see Arrgghh! My FPGA's not working: Problems with the *RTL*
- Click Here to see Eeeeek! My FPGA's not working: Problems with the *IP*
- Click Here to see Oooof! My FPGA's Not Working: Problems with *Synthesis Gotchas*
On the off-chance you aren’t familiar with GateRocket’s technology, let me briefly elucidate (don’t worry, I’m a professional, but don’t try elucidating at home without a safety net).
The RocketDrive is about the size of a hard disk drive that plugs into a slot in your tower computer workstation. Your RocketDrive would contain the largest FPGA from whichever Altera or Xilinx family you are using. Meanwhile, the RocketVision software runs on your workstation.
Suppose you have the RTL for your design, which comprises say 100 functional blocks. You might start by verifying the entire design in a software simulator, but only for relatively few cycles because software simulators are really slow when it comes to today’s humongous designs.
What happens if you now move the whole design into an FPGA on a regular development board and it doesn’t work as planned? How are you going to debug your design? This is where GateRocket comes into the picture…
Let’s assume that you have some “known good” blocks from a previous design. In this case you might use RocketVision to “move” these blocks over in to the physical FPGA in the RocketDrive. When you next run your simulation, RocketVision ensures that the part of your design in the software simulator domain plays nicely with the portions of the design that are in the real FPGA.
Moving even a few blocks over into the RocketDrive significantly speeds up your software simulation – the more blocks you move over the faster it goes.
Now suppose that you move a block over into the RocketDrive (perhaps an IP block from a third-party vendor) and the simulation fails. In this case you can use RocketVision to re-run the simulation using a copy of that block in the software world and a copy in the FPGA and to compare the interface signals (and selected internal registers and signals if required) to quickly determine when discrepancies appear.
Personally I thought all of this was brilliant. I had no clue that GateRocket were struggling. The Summer 2011 issue of Xcell Journal
just came out. It contains an article from GateRocket about the testing of high-speed serial I/O. I had only just finished reading that article (thinking “Great Job, GateRocket”) when I saw Brain’s blog…
Now I’m wearing my sad face…
This was a great company with great technology – and they offered a unique flavor of FPGA verification. I can’t believe (a) that they are gone and (b) that either Altera or Xilinx won’t absorb them into the respective Mother Ship.
Goodbye GateRocket, we hardly knew ye…
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