Smaller geometries and topology techniques have reached the point of diminishing returns
I read R. Colin Johnson’s article, “Energy efficiency may require ‘cool factor’” (EE Times, June 28, 2011, see here), covering a recent energy and semiconductor panel that debated smarter energy efficiency – a topic that it is, without doubt, one of the most fundamental and important issues facing us today.
When asked “What is the biggest hurdle to action?” these diverse expert panelists seemed to agree that, in fact, it is simply the human condition. Their opinions on overcoming this hurdle diverged a little; some preferring to alter human behavior through education, incentives or punitive measures. Others preferred to put the onus on technology itself by making products inherently efficient in-and-of-themselves. All conceded that the real answer lay in a combination of these factors.
However, while all are valid arguments, I believe that the biggest hurdle to smarter use of energy is in fact our inability to challenge the status quo when it comes to technology choices. We sometimes choose inherently inefficient technology because of comfort and habit. What do I mean? Let me use chip design as an example.
Semiconductor companies spend millions of dollars annually in the quest for low power. Unfortunately, the majority of the R&D dollars go towards exploiting the last picowatt of power from existing circuitry, instead of changing the underlining technology to be more power efficient. For decades, semiconductor technology has followed Moore’s Law.
I propose that it now follows a law of diminishing returns. State-of the-art semiconductors in production today have progressed to a feature size of 28 nanometers, yet processor chips still require performance de-rating curves, elaborate power-saving schemes and costly heat sinks and fans.
Why? The answer is because we are not addressing the root of the problem: the architecture itself. We are just finding ever-increasingly creative ways to accommodate its shortfalls.
The semiconductor industry faces the basic issue: how to challenge the status quo. An alternative lies in a fundamental change at the architectural level of processors: which are controlled synchronously from a central clock.
Put simply, this clock provides a heartbeat that synchronizes all internal operations – pretty fundamental! This clock has to be distributed to all points within the processor. This is no trivial matter in devices clocking in excess of 3 GHz. Fast clocks consume power, radiate interference and consume considerable chip real-estate. The status quo in the processor industry is the synchronous distribution of the system clock despite the fact that so much power is wasted.
So what is the alternative? One is to change from a synchronous circuit architecture to an asynchronous one. At once, power consumption, silicon real-estate, and a whole raft of lay-out and timing-closure issues can be mitigated by moving towards the asynchronous system. In such a scheme, there is no central clock; all the internal elements are responsible for their own timing.
Yet try to approach a processor designer with the idea of asynchronous. Chip designers are used to making synchronous circuits and fear the change of the status quo.
However, there are some companies in the semiconductor industry daring to tread the path least travelled. These companies are looking for major leaps in performance – not incremental improvements – and these benefits can be staggering. In a typical video-server application using an asynchronous digital signal processor (DSP), power consumption can be reduced by up to 62%.
The technologies to make a difference already exist, but the question is, are we ready to take the leap and embrace them?
About the author
James Awad has more than 12 years of experience in telecommunications and is currently director of marketing for Octasic Inc. (Montreal, Canada). Awad received his B. Eng from Concordia University in Montreal and has a strong background in ASIC design and system architecture for media processing over packet networks. While at Octasic, he has developed expertise in echo cancellation, voice and video quality.