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Dynamic reprogrammability seems rather static

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mr_bandit
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re: Dynamic reprogrammability seems rather static
mr_bandit   8/26/2011 1:25:36 AM
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This same concept was obvious to me when FPGAs first came out. Either case: the system detects a change (ie an event, like a normal state machine), and loads the code to handle the case; or generates the code on-the-fly as a function of several inputs - both tables and chunks of logic. Two FPGAs could ping-pong back and forth. This is similar to swap or dynamic load areas on early DOS systems, where there was not enough memory to hold all code. Particular functions/mini-programs would be dynamically swapped in to execute, then free up the area when done. These areas had a specific name I cannot remember right now. (A specific example was the DOS used on the Signetics TWIN and TEK 8001/8002 ICE systems - the same machine, different generations.) Since C variants are becoming more wide-spread for FPGA programming, the on-the-fly is becoming closer to reality. One concept is something similar to YACC, ie feed a on-the-fly generated table of some sort to a code generator (as one feeds BNF to YACC), which generates the C code, which is then compiled and fed into another FPGA or portion of the same FPGA. BTW - I hereby publicly put this into the public domain. If you see a patent on the concept, please fight it. (I am sure the same concepts occurred to others, and the article/comments heavily imply when they do not explicitly state the concepts. Just tired of patents on prior art and obvious stuff...)

BobC_
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re: Dynamic reprogrammability seems rather static
BobC_   8/23/2011 12:03:32 AM
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I've been hungrily monitoring this concept for over a decade, trying to conceptually map real-world problems to dynamically cooperating hardware and software solutions, waiting for the required technologies to converge and mature. The first problem is that FPGAs are still too awkward to use from the perspectives of design implementation and of operating system utilization. I believe the entire process must evolve to the point that a moderately capable embedded/real-time developer such as myself (a Computer Engineer) can do the whole basic process, soup-to-nuts, with a high-end EE needed only for optimization. To do this, the FPGA design process must evolve to be closer to current software development norms. In particular, the test environments for the hardware and the software components must be close to identical: The test harness used to test a software function must also be used to test its hardware doppelganger, the only permitted differences being in the timing domain. And, ideally, the language used to create the test harness should be the same one used to create both the software and hardware implementations. Perhaps different code for each, but the same language. Impossible? Not any more! I recently stumbled across MyHDL, a Python-based HDL that uses a restricted Python for the HDL, and unleashes the full power of Python for the test harness. And it emits both Verilog and VHDL for feeding to conventional FPGA toolchains. Similarly, the PyPy project permits Python to run at speeds equivalent to native C++. Yes, Python! Now you can code a complete cyborged application in Python, both the software, hardware and test system. I have just started down this path, studying MyHDL and ordering an FPGA development board. What do you think? Are you ready to have an entire hardware-software application be Python Powered (tm)?

BrianBailey
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re: Dynamic reprogrammability seems rather static
BrianBailey   8/22/2011 11:17:27 PM
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This is a slightly different and lessor form of reconfigurability. The configuration here is basically fixed at design time. Then we take the design through a bunch of steps and finish up with a design that does not change from that point onwards. Because an FPGA is used, we do have to configure it as part of the "boot" procedure, but after that the FPGA does not get modified during operation. On my axis this would be termed configurable. Now it is also possible that some of the IP blocks used may also be programmable, such as a communications controller and these setup parameters could be changed during operation. For full dynamic configuration I mean that part of the FPGA will get reloaded with completely different functionality during operation.

bpadalino
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re: Dynamic reprogrammability seems rather static
bpadalino   8/22/2011 10:09:04 PM
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I believe we will be seeing this more and more, especially with hard ARM cores with AMBA being the high speed interconnect. More importantly, you won't need to verify twice. You verify once in C, and let your ESL tool take your functions and make the appropriate hardware out of it. You get fast simulation speed (in C) and the FPGA vendor proves out their system loading capability. In something like linux, imagine the FPGA loading happens before the program ever starts in some crt0.s - then depending on which parts are loaded into the FPGA, those parts are hardware accelerated. I believe you'll see Xilinx really attacking this hard - especially with the purchase of AutoESL and their AutoPilot tool. For these systems, where the IO doesn't matter and the computational power does, PCIe or close AMBA will be used for communication, and everything will be transaction level modeling. I am surprised this isn't being worked on right now with all the PCIe add-in cards you can see with FPGAs. It's the first step in customized hardware acceleration.

BrianBailey
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re: Dynamic reprogrammability seems rather static
BrianBailey   8/22/2011 10:03:38 PM
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But I don't see why debug should be a nightmare. It is no different than if you verified the function in an FPGA to begin with, or debugged it in software. Then if a bug is found in the hardware version of that function, it can be fixed with a download, or flagged to not run in hardware.

Max The Magnificent
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re: Dynamic reprogrammability seems rather static
Max The Magnificent   8/22/2011 9:55:43 PM
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Hi Brian -- I totally agree -- I think dynamic reprogramability (which I take to be the ability to reprogram specific portions of an FPGA while the rest performs its task) is full of potential ... like an algorithm implemented in hardware that fine-tunes itself to better match the profile of the data it's seeing ... but I can also see why it would be such a pain from the perspective of the folks who create the design tools ... and the thought of debugging such a design makes my eyes water :-)

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