A revision to the DFI standard promises faster memory access and support for DDR4 memory sub-systems. Cadence also announced availability of supporting IP.
DFI helps speed up the memory sub-system
In a world where chip designs have to be turned around at ever increasing rates, each aspect of the design has to be standardized wherever possible. This means that the attention of the engineering group can be focused on only those aspects that provide real value. Today we hear about another of those standards getting a makeover with the promise of faster memory access.
The DFI Technical Group is a standards organization comprised of leading semiconductor companies. The specification defines an interface protocol between memory controller logic and PHY interfaces for DDR4 memory sub-systems. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. For those not quite so in the know, that means it sits between the memory controller and the high-speed pin drivers. Those pins and the connection to the memory itself conform to the DDR specification.
DFI 3.0 defines methods for interfacing to DDR4 devices with proposed data rates up to 3.2 Gbits/second per pin – more than 50 percent faster than the current DDR3 standard – and extends the low-power interface that was introduced with DFI 2.1. By accounting for frequency and power challenges at high speeds, the new specification helps ensure exceptional performance in systems using DDR4 memory.
“As the complexity of the DDR SDRAM interface increases, the DFI specification greatly enhances designers’ experiences with subsystem integration,” said Derrick Butt, principal engineer, Network and Storage Products Group at LSI Logic. “As one of the early adopters and contributors on DFI standards, LSI has greatly reduced the memory interface subsystem development effort for our customers. LSI will continue to work with industry experts on the committee to enable customer success.”
Cadence also announces IP availability
In order to help get designs ramped up, Cadence has announced support for the standard as part of its DDR DRAM Controller IP and PHY IP.
“Our customers require DFI-compliant design and verification IP that will enable them to be first to market with next-generation SoCs that support the emerging DDR4 standard,” said Marc Greenberg, director of marketing, SoC Realization, Cadence. “Our close working relationship with the DFI Technical Group ensures that we offer integration-ready DFI solutions when the specification becomes available.”
Cadence says that over 400 designs are using their DDR controllers and PHYs, and all DDR3 designs currently in development use the DFI interface.
More information about the DFI specification, its community, activities and how to participate can be found here.
Brian Bailey – keeping you covered
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