There are many news stories out every week that are interesting, but on their own don't warrant a full writeup. This is a roundup of such information...
This is a roundup of news or activities in the past few days that may be of interest to people.
Altior has announced AltraFlex™, a Compression-Decompression File System (CeDeFS) Accelerator solution, which uses the industry-standard GZIP/GUNZIP data compression/decompression protocols to increase disk space and boost disk capacity utilization, seamlessly and transparently. It combines high performance data compression, advanced hardware acceleration technology, and device drivers for high-density primary storage.
Sonics has announced SonicsGN™ (SGN), the industry's first GHz network-on-chip (NoC) for advanced, concurrent applications processing and system-level design. As the industry's highest frequency NoC available today, SGN allows SoC designers to deliver high-performance, simultaneous application processing for smart phones, mobile video and tablets. SGN will be generally available this November.
Cadence has sold some stuff to Fujitsu Semiconductor in the area of design-for-manufacturing (DFM) technologies for its 28-nanometer ASIC and system-on-chip (SoC) mixed-signal designs. They also sold other stuff to Giantec Semiconductor Corp tape, who used it to tape out a memory product for a low-power micro-controller used in its smart cards, intelligent energy meters and consumer products. It provided them with a 30% productivity boost compared to what they used before.
Dassault Systemes and Cadence are working together so that Cadence designers can use DS’ ENOVIA DesignSync within the Cadence environment to better manage semiconductor design data and improve global collaboration on designs. DS has a similar arrangement with Synopsys.
Mentor Graphics and NuFlare Technology, Inc. have announced an extension to their collaboration on integrated hardware and software solutions for advanced IC mask generation. They say that the new joint marketing and support agreement will help ensure seamless interfaces, high mask fidelity, fast mask writing times, and very high levels of technical support.
Cadence has announced that Altis Semiconductor, a European specialty foundry, standardized on the Cadence® MaskCompose Reticle and Wafer Synthesis Suite. MaskCompose helps enable seamless execution of multiple, critical steps in reticle and wafer synthesis, implementation, and documentation of data-intensive and expensive photomasks and wafer stepper layouts.
Atrenta will be holding a seminar next Tuesday (9/27) at Techmart entitled “Fast Track Your SoC Design”. The event starts at noon and ends with cocktails at 4PM. We’ll be discussing the various tools and flows we offer that focus on early architecture and RTL planning as well as improving soft IP quality. Suk Lee from TSMC will provide a keynote on IP quality from TSMC’s point of view. To register, or for more information, click here.
Brian Bailey – keeping you covered
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