Press releases that claim productivity improvement are a dime a dozen, but this one caught my eye and maybe there is something to it...
I have to admit that when I first started reading this press release from Cadence, I was skeptical. It claims that ST Ericsson got a 10X productivity gain just by switching to Cadence tools and flows. I almost discarded it as a piece of marketing hype because with so many press releases such as this, there is nothing to really explain where that gain came from. But as I continued to read, I realized that there could be something here. I will let you decide…
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that ST-Ericsson, a world leader in wireless platforms and semiconductors, achieved a 10x productivity gain by using the Cadence® mixed-signal solution. By deploying the latest release of the Cadence Virtuoso® unified custom/analog flow (6.1) for complex custom, analog and mixed-signal design, and the Cadence Encounter® unified digital flow for low-power, mixed-signal implementation, ST-Ericsson successfully taped out a CMOS 40-nanometer integrated mixed-signal IC for the high-volume mobile phone market.
"The result from ST-Ericsson demonstrates that the enhancements and improvements we have implemented deliver a truly unified mixed-signal flow and help our customers master today's complex mixed-signal designs both predictably and efficiently," said Qi Wang, group director, Solutions Marketing at Cadence. "Our mixed-signal solution embodies the tenet of the EDA360 vision and delivers on our end-to-end approach to Silicon Realization."
To accelerate the design and verification task of its analog, RF, memory and mixed-signal SoCs, ST-Ericsson chose Virtuoso Analog Design Environment XL, a multi-testbench environment that automates the verification process to ensure spec compliance. To cut simulation run time, the company deployed the award-winning Virtuoso Accelerated Parallel Simulator for analog block-level simulation as well as the analog solver within the Cadence Virtuoso AMS Designer, for high-performance, mixed-signal, full-chip verification.
"Using the Cadence mixed-signal solution enabled us to accelerate our design time by 10x compared with the design of a previous chip built in 65 nanometers," said Rolf Becker, development manager at STE. "We saw significant advantages resulting from our use, for the first time, of OpenAccess as the single database. Any design change that was done by one designer was immediately visible to the rest of the global design team without doing lengthy stream-out/stream-in operations, and we were amazed how much time was saved."
OpenAccess, the industry standard database, helped boost productivity during the implementation phase by enabling a seamless collaboration and data transfer between the analog and digital design teams. Virtuoso Layout Suite XL, fully connectivity-driven in combination with the Virtuoso Space-Based Router, helped ST-Ericsson to significantly speed up the physical design.ST-Ericsson also used Cadence QRC Extraction, a parasitic extraction technology for analog device-level and mixed-signal interconnect extraction, and the Cadence Encounter Digital Implementation System for RTL-to-GDSII implementation, as part of a new mixed-signal-on-top design methodology, that was pivotal for the successful tapeout.
Brian Bailey – keeping you covered
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