This is a roundup of news or activities in the past few days that may be of interest to people.
Jasper Design Automation has announced that Coby Hanoch has joined the executive team as Vice President of International Sales to manage sales activities outside of North America. "Jasper is growing at a tremendous rate," said Kathryn Kranen, President and CEO of Jasper. "Having worked with Coby for many years, I am confident he has the right drive, talent, and experience leading multi-national sales organizations to lead Jasper's global growth."
Numetrics has announced a multi-year agreement with the Automotive Product Group (APG) of STMicroelectronics. APG will apply the Numetrics’ software as part of a broad initiative to continue to ensure world-class product development productivity and schedule predictability.
Symtavision has launched SymTA/S 3.0 and TraceAnalyzer 3.0, a fully integrated version of these system-level tools for model-based design and trace-based verification. Targeted at automotive, aerospace, automation and other performance- and safety-critical systems, the combination of SymTA/S 3.0 and TraceAnalyzer 3.0 enables efficiency and reliability for the dimensioning, optimization, regression-testing, and verification of controllers and networks, focusing on load, task and message latencies, system schedulability, end-to-end timing, data consistency and other key properties that ensure system correctness.
EMA Design Automation has announced the release of five PCB design productivity applications to be available inside the Cadence® Design Systems OrCAD® Capture Marketplace. The new CircuitFit app is derived from EMA’s CircuitSpace product and allows the design engineer to perform early fit analysis at the schematic level prior to committing the design to placement and layout. CIP in CIS, allows OrCAD users to access EMA’s popular Component Information Portal (CIP) software inside OrCAD Capture CIS. Three other apps all came directly from customized code written to satisfy specific customer needs. More information can be found here.
Duolog Technologies, is partnering with Cadence to present a joint webinar featuring automated solutions to many of the problems commonly associated with HW/SW integration. The webinar, scheduled for October 11th (9AM Pacific), will feature an interactive demonstration of a complete design and verification environment implemented using the Duolog Socrates and Cadence Incisive Enterprise Simulator products. Click here to register.
Synopsys has announced advances in its Galaxy™ Implementation Platform with the availability of its unified solution for mixed-signal designs. The new unified solution provides seamless integration between IC Compiler physical implementation and the Galaxy Custom Designer® solution, allowing design teams to easily move between digital and custom implementation flows while maintaining design data integrity. The unified solution accelerates the design development cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development, including the time-critical tapeout phase. Didier-Jerome Martin, physical implementation manager at STMicroelectronics' Microcontroller Division says "Using Synopsys' unified physical implementation solution on a 32-bit microcontroller design we reduced the cycle time by 25 percent from initial floorplanning to final tapeout, as compared to our previous flow. We also experienced a 2X productivity gain when performing late-stage layout ECOs, at a time in the project when schedules were compressed and time was at a premium."
Altera has announced the availability of the industry's first Serial RapidIO® Gen2 FPGA based solution, enabling improved bandwidth and link flexibility for next-generation 3G and 4G wireless base station deployments. Altera successfully interoperated its RapidIO MegaCore® Function IP core implemented in a Stratix® IV GX FPGA with a Serial RapidIO® Gen 2 switch from Integrated Device Technology (IDT). Altera's proven Serial RapidIO Gen2 solution increases system bandwidth by providing a 20-Gbaud packet-based interconnect for linking radio cards, host processors and digital signal processors used in high-performance communications systems.
Synopsys has announced availability of the latest release of its Synplify Pro® and Synplify® Premier FPGA synthesis tools. The new Synplify tool release enables engineers to build higher reliability into their FPGA designs through a new feature that provides automated creation and preservation of error-correction logic, including safe finite-state machines (FSMs). Additionally, an enhanced interface for the tool allows designers to track progress and analyze synthesis results hierarchically. For ASIC prototypers, support for Synopsys DesignWare® Library MacroCell IP has been added, broadening DesignWare IP support and improving compatibility with Design Compiler®.
HDL Design House is a supplier of design IP related to MIPI standards and has announced new design IP products such including
• DSI Host IP core (HIP3500), compliant with MIPI DSI v1.02
• DSI Periph IP core (HIP3510), compliant with MIPI DSI v1.02
• UniPro IP core (HIP3600, compliant with MIPI UniPro v1.40
Brian Bailey – keeping you covered
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