Cadence Design Systems has announced that it has collaborated with TSMC to provide mutual customers access to a library characterization reference kit. The Cadence® Library Characterizer (Altos Liberate) reference kit for TSMC's standard cell libraries is now available to TSMC customers for download on TSMC-Online. The reference kit, along with the Cadence Library Characterizer technology, enable customers to re-characterize their standard cell libraries in-house, on their own schedule with the same characterization technology and setup used internally at TSMC, delivering better consistency.
Sidense Corp., a developer of Logic Non-Volatile Memory (LNVM) one-time programmable (OTP) memory IP cores, announced today that it has raised an additional $5.6 million for its Round C financing from several sources, including one new source, Ontario Emerging Technologies Fund (OETF). Also participating in this round of funding are existing Venture Capital investors including Tech Capital Partners, VentureLink, and Vertex Venture Capital.
A whitepaper from ASSET InterTech describes a new method for validating, testing and debugging circuit boards by embedding a board-tester-in-a-chip. The method, known as FPGA-controlled test (FCT), involves the automatic insertion of multiple embedded instruments into a field programmable gate array (FPGA) to function as a board tester. The embedded board tester is then operated from an intuitive drag-and-drop graphical user interface.
Download interface is here
SpringSoft has announced that Advantest Corporation, a leading supplier of semiconductor test equipment, has signed a multi-year renewal agreement expanding its deployment of SpringSoft’s Verdi™ Automated Debug System. Advantest will apply the Verdi software to verify register transfer level (RTL) designs synthesized by behavior synthesis tools in its enhanced electronic system level (ESL) design flow. Shinya Sato, manager of the Design Engineering Department at Advantest said “Verdi helps our engineers to meet time-to-market and quality goals. Using Verdi’s tools, we have built an advanced ESL C-to-RTL synthesis methodology to achieve higher engineering productivity. We believe that Verdi can be especially helpful in verifying synthesized RTL with this new methodology flow.”
NanGate has announced that Fujitsu Semiconductor Limited has adopted NanGate’s Library Creator, a tool set that enables efficient creation and validation of digital cells, and NanGate Design Optimizer, an IC analysis and post-route optimization tool, into its advanced 28nm design environment. We are impressed with the effectiveness of NanGate’s solution to automate generation of large sets of complex cells, and the ability to improve the quality of design performance,” said Hiroshi Ikeda, Director of System LSI Technology & Product Department, Technology Development Division, IP & Technology Development and Manufacturing Unit of Fujitsu Semiconductor Limited.
Synopsys has announced that Chongqing Chongyou Information Technologies Company, Ltd. (CYIT), a supplier of mobile terminal technology and product solutions for China's 3G mobile networks, taped out its first 65 nanometer, dual-mode baseband, low-power device within five months – significantly ahead of the original schedule – using the Synopsys Galaxy™ Implementation Platform. To meet the stringent low-power requirements of the GSM/TD-SCDMA market, CYIT implemented advanced low-power techniques including multiple power domains with shutdown, and used IEEE-1801 Unified Power Format (UPF) to specify the power intent. Following this accelerated tapeout, CYIT has deployed the Synopsys solution for the implementation of all future low-power ICs.
To address the design's multiple multi-voltage blocks, CYIT utilized a hierarchical low-power flow with power intent definition described in UPF. Synopsys Professional Services assisted in designing the production chip using the Synopsys Lynx Design System. This approach allowed the CYIT engineering team to implement and deploy this flow with ease, resulting in the speedy completion of a production-ready design within five months.
Arasan Chip Systems has announced the availability of its USB 2.0 PHY IP. The USB 2.0 PHY comprises a complete on-chip physical transceiver solution optimized for low power consumption, minimal die area, and high data throughput. The USB 2.0 PHY features fully integrated Electrostatic Discharge (ESD) protection, full support for OTG, device, hub and host functionality. The core was developed by Mentor Graphics Corporation and proven in silicon in the SMIC 130nm process. Arasan has licensed the complete core and associated technology from Mentor Graphics and Arasan will support and develop the technology using its own analog mixed signal design team.
SpringSoft and Vennsa Technologies have announced interoperability between SpringSoft’s Verdi™ Automated Debug System and Vennsa’s OnPoint™ Root Cause Analysis. Enabled by the SpringSoft Verdi Interoperability App (VIA) platform, the integrated solution allows engineers to increase verification productivity and dramatically slash the chip debug burden. “Error localization and debugging consume more than 60% of the verification effort,” remarks Andreas Veneris, president and chief executive officer of Vennsa Technologies. “Verdi is the de facto standard debugger and a verification engineer’s tool of choice. Tight integration between OnPoint and Verdi using SpringSoft’s VIA platform provides the user community with the best solution for failure analysis that OnPoint offers coupled with the powerful visualization environment of Verdi.”
Brian Bailey – keeping you covered
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