This is a roundup of news or activities in the past few days that may be of interest to people.
Open Core Protocol International Partnership (OCP-IP) announced today they have published an updated version of their Research Bibliography. This innovative feature of the OCP-IP website allows both students and researchers to quickly and easily locate critical research documents and papers for use in studies and research projects in the field of on-chip communications.The Research Bibliography was updated through the efforts of the OCP-IP NoC Benchmarking Working Group and is freely available to anyone who wishes to view the document. The Group includes: Tampere University of Technology, Royal Institute of Technology (KTH), Boston University, University of British Columbia, Carnegie Melon University, Princeton, Washington State University, and Transylvania University.
Mentor Graphics has announced its third generation Nucleus® Real Time Operating System (RTOS). The Nucleus product adds built-in power management capabilities that seamlessly use hardware features such as Dynamic Voltage and Frequency Scaling (DVFS), making it ideal for power conscious, battery powered applications. New Nucleus connectivity features include a certified "IPv6 Ready" networking stack and security protocols, as well as a variety of wireless communication options such as Wi-Fi, Bluetooth, and Zigbee to enable faster time-to-market when developing connected devices.
Synopsys has released a new version of their Synphony high-level synthesis tool. The new Synphony Model Compiler release, introduces new features for both the FPGA and ASIC flows. The new features include:
- RTL Encapsulation – you can now embed RTL in your high-level model and simulate the complete system in Simulink without the need of external simulators. This enables very high simulation performance while using interface IP, 3rd party IP, and legacy RTL IP in your Synphony Model Compiler designs.
- 10 new IP blocks: including Cyclic Redundancy Check (CRC), Pseudo-Noise Generators, and more.
- New IP Optimizations: FIR now has an additional architecture choice which has significant area and performance improvements on certain target technologies, especially ASIC.
- High-level synthesis optimization controls are now available for Folding and Pattern Folding.
- HLS Subsystem block has some QoR and usability enhancements.
announced they have collaborated to deliver emulation solutions for the verification of Multi-Gigabit Ethernet Systems-on-Chips (SoCs). The combination of the Mentor® Veloce
® hardware emulation technology and the iSolve
TM application solutions with MoreThanIP’s Ethernet 40G/100G MAC / PCS IP Cores, delivers a high-performance and productive environment for handling the verification of up to hundreds of Ethernet ports associated with switch and router SoCs. The goal of both companies is to help bring complex telecom SoC designs to market on schedule, without compromising verification accuracy or performance.Open-Silicon
has announced the launch of its ARM® Center of Excellence. The new engineering group will focus on providing complete SoC development solutions for low-power chip development to the networking, telecommunications, storage and computing markets. To enhance the offering, Open-Silicon partnered with ARM through a comprehensive multi-year licensing agreement for the ARM® product portfolio.NextOp
Software has announced that Craig Shirley has joined the company as vice president of worldwide sales. Mr. Shirley will lead the company's sales organization to extend its leadership in assertion-based verification software. With over 20 years of executive sales and technical management experience, Mr. Shirley most recently served as Apache Design Solutions' vice president of worldwide sales, achieving a compound annual revenue growth rate of over 25% during his tenure. Prior to Apache, Mr. Shirley was vice president of worldwide sales and support at Jasper Design Automation. Mr. Shirley also served as vice president of North American sales at Verisity Ltd., where he scaled the worldwide sales process to drive the startup to become a $70 million company and the best performing IPO of 2001. Prior to Verisity, Mr. Shirley held various sales management positions within the EDA industry. Mr. Shirley graduated with honors from Auburn University with a Bachelor of Science degree in computer engineering.Numetrics
, a provider of fact-based resource & schedule trade-off analysis tools for semiconductor integrated circuit (IC) development projects, has announced that Cypress Semiconductor Corp
. has deployed Numetrics’ tools and industry database to perform root cause analysis and benchmark its new product development capability against the industry. Cypress’ goal is to ensure its rapidly expanding PSoC product line consistently achieves on-time market delivery and quality within development budget targets. “We were able to use Numetrics solutions to perform root cause analysis and benchmark key performance indicators, including productivity, cycle time, schedule performance and spin count to drive systematic changes that significantly improve our product development processes,” said Paul Keswick, EVP of New Product Development at Cypress. “The ROI is getting our products to market faster or with fewer resources, or both.”The Portland Group
, a wholly-owned subsidiary of STMicroelectronics
and a supplier of compilers for high-performance computing (HPC), today announced its products now include support for the upcoming microprocessors from AMD (NYSE: AMD) based on their "Bulldozer" architecture. The "Bulldozer" core architecture uses a flexible floating point unit called the Flex FP that can simultaneously execute two 128-bit commands or one 128-bit and one 256-bit command. The powerful floating point unit is included in the upcoming 16-core processors codenamed "Interlagos" intended for high-performance servers. Additionally, "Interlagos" delivers a rich mix of features targeting complicated, multi-threaded HPC environments.
– keeping you covered
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