This is a roundup of news or activities in the past few days that may be of interest to people.
Digital Core Design has introduced the DQ80251 core which they claim is the World’s fastest solution based on Dhrystone 2.1 benchmark tests, and is up to 56.8 times faster than the original 8051 at the same clock frequency. The core provides up to 0.54311 DMIPS/MHz (VAX MIPS) and uses only 14 500 ASIC gates. The DQ80251 family is available as VERILOG Source code, VHDL Source code and FPGA Netlist formats.
DMAP has released PCI Express and Ethernet (Gigabit, 10G) IP for DO-254 applications that has been verified using SystemVerilog and Assertion Based Verification (ABV) in an OVM environment. Adherence to DO-254 compliance during development, and verified using advanced verification methods supported by Mentor Graphics industry-leading Questa® functional verification platform, ensures thorough testing of these complex IP devices. DO-254 explicitly requires functional coverage, a verification approach that ensures all requirements have been covered in the designed hardware. The DO-254 standard states the following: "Evidence is provided that the hardware implementation meets the requirements" [DO-254 6.2.1-1]. Regardless of the level of design (LRU, board, device, IP) and design assurance level (DAL) of the item, functional coverage is the fundamental metric of every ‘safe' design flow.
Mentor Graphics and JEOL have announced an agreement to collaborate on integrated hardware and software solutions for advanced IC mask writing. The companies are currently engaged in a research program to demonstrate the feasibility of an innovation called multi-resolution writing for shot count reduction of up to 30% compared to the conventional writing technique, dramatically reducing mask writing time. The new agreement is focused on developing this technology as well as providing optimized interfaces between the Mentor® mask data preparation and mask process correction (MPC) software and JEOL e-beam lithography equipment.
Magma has announced that since its release 18 months ago, Tekton has grown its customer base to more than 25 companies, achieving the fastest adoption rate of any tool in the company’s history. Tekton, they claim, is the most advanced sign-off-quality static timing analysis (STA) tool on the market, and was introduced to the industry in the spring of 2010. They say that this unprecedented growth was accomplished despite the chip industry’s shrinking electronic design automation (EDA) budgets and designers’ historical unwillingness to change sign-off tools. The key is supposedly Tekton’s concurrent multi-mode, multi-corner (MMMC) analysis and multi-threaded architecture which can save tens – if not hundreds – of hours over the span of numerous ECO loops.
Brian Bailey – keeping you covered
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