eSilicon, Synopsys, Mentor, Duolog, Arasan and Renesas made the lineup today. See here for their news...
This is a roundup of news or activities in the past few days that may be of interest to people.
eSilicon Corporation has made some significant changes in its management and board. They have announced the appointment of Seth Neiman as chairman of the board and the addition of Willem "Wim" Roelandts and Timothy Chen to its board of directors. This would seem to be a change made by their venture capitalists. Seth Neiman is a managing partner of Crosspoint Venture Partners. Neiman has served as a board member of a number of leading public broadband networking companies, including Brocade Communications Systems, Foundry Networks, Avanex, and iPass. Prior to Crosspoint, Neiman spent 17 years as an entrepreneur and executive in both start-ups and Fortune 500 companies. Timothy Chen is a partner at private equity firm GL Capital Group. He is also the economic advisor to the provincial government of Jiangsu, China. Before joining GL Capital, Chen was CEO of the NBA China. Prior to his work with the NBA China, Chen was with Microsoft as a corporate vice president and CEO for the greater China region. He has held positions with Motorola (China) Electronics Ltd. and AT&T Bell Labs in the U.S. Willem Roelandts serves on the boards of Applied Materials, Aruba Networks and IMEC, Belgium. He is also the chairman of the advisory board of Engineering Pathways to Success at San Jose State University. Roelandts previously served as president, CEO and a board member of Xilinx. Prior to his tenure at Xilinx, Roelandts had a 30-year management career at Hewlett-Packard.
Synopsys has announced that GLOBALFOUNDRIES has certified Synopsys' IC Validator physical verification product for 28-nanometer (nm), 40-nm and 65-nm physical signoff, with immediate availability of design rule checks (DRC) and layout-versus-schematic (LVS) runsets to GLOBALFOUNDRIES customers. IC Validator, part of the Galaxy™ Implementation Platform, is an add-on to IC Compiler for In-Design Physical Verification, making it possible for place and route engineers to accelerate time to tapeout by eliminating late-stage surprises and manual fixes. GLOBALFOUNDRIES' qualification of IC Validator brings the benefits of In-Design Physical Verification to design teams working with GLOBALFOUNDRIES' 28-nm, 40-nm and 65-nm process nodes.
Mentor Graphics has announced a combined technology for thermal characterization and simulation with T3Ster® hardware test products and its FloTHERM® software. The Mentor Graphics® T3Ster product is a thermal transient tester for semiconductor device packages and LEDs. Mentor’s FloTHERM product is used for electronics thermal simulation and analysis to predict airflow, temperature and heat transfer throughout electronics equipment including components, boards, and entire systems. The unique interface between T3Ster and FloTHERM creates accurate thermal simulation models. The thermal characterization offering is JESD51-14 compliant. Mentor says that increased design complexity and smaller form factors create heat management problems which represent one of the biggest challenges in electronics today. Temperature is understood to be the key accelerator in the majority of reliability failures and IEEE Standard 1413 recognizes the need for accurate thermal data at all levels of a system’s implementation.
Duolog Technologies has announced that semiconductor industry veteran and SystemC guru, Jack Donovan, has joined the Duolog team. Based in the company’s Galway, Ireland office, Donovan will focus on further expanding the capabilities of Duolog’s Socrates tool suite in the ESL and TLM domains. Jack joins Duolog with more than 30 years of experience as a manager and leader of engineering teams. He is a well-known consultant in the EDA industry for his SystemC and TLM 2.0 expertise and is co-author of the industry bestseller, ‘SystemC: From the Ground Up’. Previously, Jack was President and a Member of the Board at XtremeEDA. During his time at XtremeEDA, he Founded ESLX, Inc. and was President before it merged with XtremeEDA. Jack has held various senior management and engineering positions at several companies in San Jose and Austin including Synopsys Inc. and Tandem Computers Jack received his MSEE and BEE from the Georgia Institute of Technology.
Arasan Chip Systems has introduced the third generation of its Hardware Validation Platform family targeted for validation of hardware and software infrastructure that comply with analog PHY based standards for serial connectivity between chips, camera and display modules, and flash storage in mobile platforms. Customers adopting emerging and existing protocols like MIPI’s Unipro, CSI-2 and DSI, JEDEC’s UFS and SDA’s SD4.0 can use Arasan’s platforms to jump start their pre-silicon, silicon and system validation and applications development.
Renesas has announced that it has developed a 40-nanometer (nm) memory intellectual property (IP) for automotive real-time applications. Renesas will also launch 40nm embedded flash microcontrollers (MCUs) for automotive applications using this 40nm flash technology with samples available by the beginning of autumn 2012. Products use a MONOS (metal oxide nitride oxide silicon) technology which according to Renesas provide excellent characteristics for three critical parameters (data retention, program/erase cycle endurance and programming time) The flash memory IP guarantees 20 years of data retention, and can be read from up to 170? junction temperature. Additionally, the code flash supports read speed of 120 megahertz (MHz), and the data flash achieves data-retention of 20 years even after 125,000 of program/erase cycles.
Synopsys and Global Unichip Corporation have announced that GUC has achieved more than one gigahertz frequency on a dual-core ARM® Cortex™-A9 MPCore™ processor with Synopsys IC Compiler. The five-million-gate, dual-core ARM Cortex-A9 processor, intended for high-end digital television chips, was fabricated on a TSMC 40nm low power process. It achieved a signoff frequency of 1 GHz at the worst process corner and 1.3 GHz at the typical process corner, without requiring the use of overdrive voltage. GUC used the Synopsys Galaxy implementation methodology to overcome the design challenges associated with achieving this level of operating frequency and power, including:
- Sensitivity of high-performance designs to memory macro placement, making it difficult to meet timing between the memories and processors
- Placement of register banks for improved frequency and routability, often requiring support for structured placement techniques
- High utilization in excess of 80 percent, requiring timing and congestion to be managed from the outset, starting with synthesis through place and route
- Tight skew and latency requirements for clock distribution network.
– keeping you covered
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