The Design Automation Conference is a pretty significant event for the EDA industry and if you haven't got your name on the program yet, there are still a few opportunities...
It is important to be at DAC, but one thing that is even more prestigious is to have your name on the program. So, it is too late to get a paper submitted and accepted, but there are other ways that just might tickle your fancy.
There are three deadlines coming up for DAC
1. The DAC User Track submission deadline is January 17
The User Track is a forum for design professionals to share their work with other experts. DAC invites system designers, application engineers, IC designers, design-flow developers and vendor-customer teams to submit two-page abstracts for consideration. A typical User Track contribution describes solutions to practical issues related to EDA tools in a design flow.
The User Track includes three broad topic areas: Embedded Systems and Software, Front-end Silicon Design, and Back-end Silicon Design. This inclusion of Embedded Systems and Software reflects the strong growth in Embedded System design activity. User Track presentations may be problem-specific in scope (e.g., analyzing substrate coupling during floorplanning) or may address an application domain (e.g., designing wireless handsets). Initial submissions are two-page extended abstracts—a quick and convenient format for busy professionals.
Please visit www.dac.com/usertrack for detailed User Track information and submission guidelines.
2. There is a NEW Design Contest at DAC this year. The deadline for teams is December 30.
This is the first ever EDA algorithm competition. The results will be announced two weeks prior to the 49th DAC. Creating easily routable designs is one of the key challenges for modern physical synthesis design closure tools. Numerous factors contribute to making this problem increasingly challenging with advanced process technologies. Increased (re)use of embedded IPs or memories that complicate placement and block wiring channels, non-uniform metal layer stacks designed for higher performance, the pressure to reduce die size to control manufacturing cost, and ever increasingly complex design rules. Consequently, the design closure flow needs to be aware of routability during the entire flow, especially during cell placement.
Recent years have seen significant advances in wirelength-driven placement; however, wirelength does not directly correspond with design routability. The problem is exacerbated by the lack of standard frameworks and metrics to evaluate the routability of a given placement. To help further advance the state-of-the-art in placement, DAC is sponsoring its first contest on the topic of routability-driven placement.
Please visit http://www.dac.com/routability_driven+placement+contest.aspx for full details of the competition and to register.
3. Workshop Submission Deadline, Thursday, January 19, 2012
Workshop proposals will be considered starting September 19 until January 19, 2012. Workshops will be notified by February 14, 2012 with accept or reject notification. For more information, please contact Michael McNamara, DAC Tutorial Chair.
Brian Bailey – keeping you covered
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