Conference related information, calls for papers, contributions and participation are all found here...
If you have an upcoming conference related to EDA tools, techniques, IP or design practices and would like me to include your call for papers, contribution or participation in this conference roundup, then please send me an email.
In this issue:
DVCon 2012 February 27-March 1 in San Jose, California
Calls for papers
IEEE Journal on Emerging and Selected Topics in Circuits and Systems: New Interconnect Technologies in On-Chip CommunicationIEEE Symposium on Field Programmable Custom Computing Machines
International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XII)
Workshop on Mapping of Applications to MPSoCs and International Workshop on Software and Compilers for Embedded Systems
The Advance Program for the 2012 Design and Verification Conference (DVCon), sponsored by Accellera Systems Initiative, is now available online and registration is open ( www.dvcon.org ). DVCon 2012 will be held February 27-March 1 at the DoubleTree Hotel in San Jose, California. The 2012 keynote address, "Systemic Collaboration: Principles for Success in IC Design," will be presented by Aart de Geus, Chairman and CEO of Synopsys, Inc. at 2:00pm on February 29th in the Oak/Fir Ballroom. The Industry Leaders Panel will be moderated by JL Gray, vice president at Verilab and author of "Cool Verification" and will be held Tuesday, February 28th at 2:30pm in the Oak/Fir Ballroom.
A second panel, "Build or Buy: Which is the Best Practice for Hardware-Assisted Verification?" will be moderated by Brian Bailey of Brian Bailey Consulting and will be held on Wednesday, February 29th at 3:30pm in the Oak/Fir Ballroom. Poster sessions will be held on Tuesday from 10:30-11:30am and Wednesday from 10:00-11:00am. The DVCon Expo will be open on Tuesday from 3:30-6:30pm and Wednesday from 4:30-7:00pm. For the complete schedule, including list of sessions, topics and sponsored luncheons and events, visit www.dvcon.org .
Call for PapersIEEE Journal on Emerging and Selected Topics in Circuits and Systems
Special Issue on New Interconnect Technologies in On-Chip Communication
Manuscript submission deadline has been extended to December 30th
Scope and purpose
The IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) seeks original contributions for an issue on New Interconnect Technologies in On-chip Communication to appear in June 2012. With Moore's Law and the abundant amount of computation available in multi-many-core processors, the communication is becoming the bottleneck of these systems and often determines the scalability, both in terms of cost and performance. To overcome the limitations of conventional electrical signaling communication, alternative technologies have been recently proposed and will not only impact how data is communicated but also, the system design. The purpose of this issue is to report on recent and original advances on enabling circuit and system designs related to new interconnect technologies that have been proposed and the design of onchip communication architecture that leverage these new technology.
Topic of interest
Topics of interest for this issue include, but are not limited to:
- Circuit Design
Circuit designs for new interconnect technologies, including but not limited to nanophotonics, 3D stacking, RF signaling, capacitive coupling, inductive coupling, transmission lines, as well as asynchronous communication.
- On-Chip Communication Architecture
Network-on-Chip (NoC) or other communication architectures that exploit these new interconnect topologies, including topology, routing algorithm, flow control, and router microarchitecture; as well as hybrid or heterogeneous NoC architectures that combine different signaling technologies.
- Application/System Design
Impact of new interconnect technology on system design, including on-chip cache hierarchy, CPU organization, and main memory organization. Core-to-memory communication using these new interconnect technology to extend the benefits of the technology for communication with off-chip memory.
Manuscript submissions due December 30, 2011
First round of reviews completed January 27, 2012
Revised manuscripts due February 17, 2012
Second round of reviews completed March 9, 2012
Final manuscripts due March 30, 2012
More information from firstname.lastname@example.org or http://jetcas.polito.itFCCM 2012
The 20th Annual International IEEE Symposium on Field Programmable Custom Computing Machines Toronto, Canada 29 April – 1 May 2012 www.fccm.org
The IEEE Symposium on Field-Programmable Custom Computing Machines is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware. Over the past two decades, FCCM has been the place to present papers on architectures, tools, and programming models for field-programmable custom computing machines as well as applications that use such systems. Papers on the traditional topics of FCCM as described below are solicited:
Non-Conventional High Level Compilation and Synthesis
This year we will host a special track on the synthesis of circuits from high level descriptions written in alternative languages with a focus on the compilation of programs into circuits. In particular, we wish to attract papers that show how programs may be converted into circuits rather than using an existing programming language to improve the productivity of hardware engineers (as is the case for SystemC).
FCCM will accept 8-page full papers for oral presentation, 4-¬-page short papers for poster presentation, and poster presentations not included in the proceedings. All submissions should be written in the English language. An online submission link will be available on the FCCM website starting in late December. Papers should use the formatting template linked at the FCCM website.
Title and Abstract Submission: 6 January 2012
Short and Regular Paper Submission: 6 January 2012
Notification of Acceptance: 27 February 2012
Camera-¬-ready Copy: 29 March 2012
Conference: 29 April – 1 May 2012SAMOS XII
International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XII)
Samos, Greece, July 16-19, 2012 http://samos.et.tudelft.nl/
SUBMISSION DEADLINE: February 10, 2012
SAMOS is a premier and well-established conference on embedded systems organized annually since 2001. The conference brings together researchers from academia and industry on the quiet and inspiring northern mountainside of the Mediterranean island of Samos. It provides an environment where collaboration rather than competition is fostered.
The conference considers new state-of-the-art mature research papers on all aspects of embedded processor hardware/software design and integration. SAMOS XII has IEEE technical co-sponsorship by the IEEE CAS Society (pending) and the IEEE SSCS Germany Chapter and the conference proceedings will be published in the IEEE Xplore (pending). Authors are invited to submit technical papers in accordance to the author's instructions describing original work in one of the following tracks:
Authors of selected papers will be invited to submit an extended version of their work to contribute to a special issue of the International Journal of Parallel Programming (IJPP). This issue will accept papers from all the topics of the SAMOS conference, ranging from the Applications, Systems, Architectures, and Processors Track to the Modeling, Design, and Design Space Exploration track.
February 10, 2012 -- Paper Submission Deadline
April 14, 2012 -- Notification of Acceptance
May 11, 2012 -- Camera Ready Submission Deadline
July 16 - 19, 2012 -- SAMOS XII, Greece5th Workshop on Mapping of Applications to MPSoCs and 15th International Workshop on Software and Compilers for Embedded Systems Map2MPSoC/SCOPES 2012
May 15-16, 2012 Schloss Rheinfels, St. Goar, Germany
The workshop on Software and Compilers for Embedded Systems (SCOPES) and the workshop on Mapping of Applications to MPSoCs (Map2MPSoC) will organize a joint Map2MPSoC/SCOPES workshop in 2012.
The Map2MPSoC/SCOPES workshop will feature a combination of research papers and research presentations (details see below). The research papers will also be published in the ACM digital library. The workshop will be held in cooperation with ACM SIGBED and EDAA.
AIM AND SCOPE
The influence of embedded systems is constantly growing. Increasingly powerful and versatile devices are developed and put on the market at a fast pace. Their functionality and number of features is increasing, and so are the constraints on the systems concerning size, performance, energy dissipation and timing predictability. To meet all these constraints, multi-processor systems on a chip (MPSoCs) are becoming popular in embedded systems. In order to meet the performance and energy constraints of embedded applications, heterogeneous architectures incorporating functional units optimized for specific functions are commonly employed. This technological trend has dramatic consequences on the parallelization, mapping, compiler and design technology used to develop these systems.
The Map2MPSoC/SCOPES workshop focusses on the software generation process for modern embedded systems. Topics of interest include all aspects of the compilation and mapping process of embedded single and multi-processor systems. This includes (but is not limited to):
- models of computation and programming languages;
- performance analysis techniques for models of computation;
- automatic code parallelization techniques;
- mapping and scheduling techniques for for embedded multi-processor systems;
- code generation techniques for embedded single and multi-processor
- design-space exploration techniques for use in the HW/SW codesign process;
- techniques to exploit the dynamic behavior in embedded applications;
- interactions between operating systems and compilation techniques;
- techniques for compiler aided profiling, measurement, debugging and
validation of embedded software.
The workshop structure (presentations followed by intensive discussions) allows for an interactive atmosphere in which industrial and academic representatives can exchange new ideas and trends in the area multi-processor mapping and code generation.
The workshop will take place in the beautiful “Schloss Rheinfels” hotel at St. Goar, Germany. Schloss Rheinfels is a castle at one of the nicest places within the Rhine valley, itself a world heritage site. Among a set of hotels focusing on wellness, the hotel was voted the #1 hotel within Germany in 2007. There is a beautiful view from the hotel onto the river Rhine.
Abstract submission research papers: Feb 17, 2012
Full research paper submission: Feb 24, 2012 (hard deadline)
Notification of acceptance: Mar 19, 2012
Final paper submission: Apr 2, 2012
Abstract submission research presentations: Mar 26, 2012
Notification of acceptance: Apr 2, 2012Brian Bailey
– keeping you covered
If you found this article to be of interest, visit EDA Designline
where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here
to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).