Random number generation is necessary for cryptographic processes, but how do you create a random number in an FPGA...
The other day I came across an interesting product announcement from IP Cores Inc. It was for their True Random Number Generator (TRNG).
True Random Number Generators (TRNG) are critical security blocks typically utilized to generate random numbers for secret cryptographic keys as well as seeds for pseudo-random number generators. A good-quality random number generator is essential for security, since generating the keys from a poor random source will significantly reduce the entropy of the long keys and might allow a brute-force attack on the seed that generated the key. A typical embedded application usually does not have access to high-quality randomness sources, so a designer of a System-on-a-Chip (SoC) targeting such application might want to instantiate a true-random source on the chip.
That got me to thinking about randomness, which happens in my brain every now and then. How random can a machine be? Most random number generators used in computers are pseudo-random because they are generated using a mathematical formula and thus they are predictable. For things like constrained random verification, this is a very necessary attribute – each time a certain test is run, it should produce the same set of stimulus. They get this repeatability from the seed. The seed is the first number from which the formula starts its process. But how do you ensure that the seed is random? I know some places use atmospheric noise and hardware versions may use thermal noise or some other effect based on the fabrication process variations.
But this company claims that their design works in an FPGA or that even for chip design that it requires no special handling during the physical design. So how random can the seed be? On the IP Cores website they state that the seed comes from an internal entropy source, and I know it is important for the source to be completely self-contained otherwise it could be tampered with. I have seen papers that talk about using phase noise, but these rely on external clocks or other components which makes them vulnerable. So how do you create random numbers in an FPGA?
Brian Bailey – keeping you covered
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