If you have an upcoming conference related to EDA tools, techniques, IP or design practices and would like me to include your call for papers, contribution or participation in this conference roundup, then please send me an email.
In this issue:
13th International Symposium & Exhibits on QUALITY ELECTRONIC DESIGN (ISQED 2012)
Calls for papers
ACM/IEEE Tenth International Conference on Formal Methods and Models for Codesign MEMOCODE 201215th Euromicro Conference on Digital System Design (DSD): Architectures; Methods & Tools
19th Annual Electronic Design Process Symposium
Conference Participation13th International Symposium & Exhibits on QUALITY ELECTRONIC DESIGN (ISQED 2012)
March 19-21, 2012 Techmart Center, Santa Clara, CA USA http://www.isqed.org
Keynote Speeches: Tom Beckley, Corporate Vice President, Cadence Design Systems Christophe Muller, Director & Professor, Institut Carnot STAR Dean M. Tullsen, Professor, University of California Jos Huisken, Principal Researcher, IMEC-NL
"Upholding Moore's Law by Transistor Innovations" Rafael Rios, Intel
"Design-assisted Semiconductor Manufacturing" Puneet Gupta, University of California, Los Angeles
"3D Integration with Interposer and TSVs: Requirements for technology infrastructure" Farhang Yazdani, BroadPak Corporation
"Interface Architectures for Low Power and High Performance Memory" Brian Leibowitz, Rambus Inc.
"Challenges and Opportunities of 3-D IC System Architecture and Design" Hsien-Hsin S. Lee, Georgia Institute of Technology
ISQED Technical sessions start on Tuesday 3/20 and continue until the afternoon of Wednesday 3/21. Beside plenary sessions, and workshops, the program consists of 22 technical sessions featuring near
100 papers as well as embedded tutorials on various challenging topics related to system and IC design, IP qualification, design flows, and design for manufacturability and quality. Detail program is available on the web at www.isqed.org.
Please refer to ISQED web site at www.isqed.org for information regarding the tutorials, conference, tutorials, and hotel registration.
Direct all conference inquiries to email@example.com. Early registration is recommended to take advantage of the discounted registration fee. Link to registration: http://www.eventbrite.com/event/2028963685
Call for PapersACM/IEEE Tenth International Conference on Formal Methods and Models for Codesign MEMOCODE 2012
Arlington, Virginia July 16-18, 2012 http://www.memocode-conference.com
The goal of MEMOCODE 2012, the tenth in a series of successful international conferences, is to gather researchers and practitioners in the field of the design of modern hardware and software system to explore ways in which future design methods can benefit from new results on formal methods.
Abstract submission deadline: March 2, 2012
Paper submission deadline: March 9, 2012
Notification of acceptance: May 4, 2012
Final Version for Papers: May 18, 2012
Hardware-software systems face increasing design complexity including tighter constraints on timing, power, costs, and reliability. MEMOCODE seeks submissions that present novel formal methods and design techniques addressing these issues to create, refine, and verify hardware/software systems. We also invite application-oriented papers, and especially encourage submissions that highlight the design perspective of formal methods and models, including success stories and demonstrations of hardware/software codesign. Furthermore, we invite poster presentations describing ongoing work with promising preliminary results.15th Euromicro Conference on Digital System Design (DSD): Architectures; Methods & Tools
September 5th-8th 2012 - Izmir – Turkey www.univ-valenciennes.fr/dsd2012/
The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded, pervasive and high-performance) digital and mixed hardware/software system engineering, down to micro-architectures, digital circuits and VLSI techniques. It is a discussion forum for researchers and engineers from academia and industry working on state-of-the-art investigations, development and applications. It focuses on advanced circuit and system design and design automation concepts, paradigms, methods and tools, as well as on modern implementation technologies from full custom in nanometer technology nodes to FPGA and to multi-core infrastructures.
Compiler assisted ASIP, CMP, SMP, SMT, DSP-VLIW, GPU, platform based system design research results and application analysis and parallelization for embedded hardware and software design are welcome.
Design and Verification Languages and Standards, High Level Synthesis, Efficiency, Density, Signal Integrity, Testability, Timing Analysis and Timing Closure, Asynchronous Techniques, Reconfigurable Architectures, Power Consumption, Computational Power Speed and Performance, Productive Design Technology and Engineering Flows, Manufacturability, Cost, Reliability, Error Resilience, Complexity, or Process Variability issues, Modeling, Design Experiences are covered in DSD.
T1: (RC) Programmable/re-configurable/adaptable architectures
T2: (AP-HwSw) Application analysis and parallelization for embedded and high-performance design
T3: (SHES) System, hardware and embedded software design and automatic synthesis.
T4: (SoC & NoC) Systems-on-a-chip and networks-on-a-chip.
T5: (SMVT) System, hardware and embedded-software specification, modeling, verification and test.
T6: (APP) Applications of (embedded) digital systems.
T7: (ET) Important issues introduced by emerging technologies.
SS1: (FDR) Flexible Digital Radio.
SS2: (MSDA) Multicore Systems: Design and Applications
SS3: (DTDS) Dependability and Testing of Digital Systems
SS4: (FTDSD) Fault Tolerance in Digital System Design
SS5: (SEO-WN) System-level Energy Optimization and Wireless Sensor Networks
SS6: (AHSA) Architectures and Hardware for Security Applications
SS7: (MoRPS) Monitoring and Reconfiguration of Parallel Systems
SS8: (DCPS) Design of Heterogeneous Cyber-Physical Systems
Prospective authors are encouraged to submit their manuscripts for review electronically through the following web page
(http://www.univ-valenciennes.fr/dsd2012/) or by sending the paper to the Session Chair via email (firstname.lastname@example.org) only if an unexpected web access problem is encountered) before the deadline for submission.
Submission of papers: March 12th, 2012
Notification of acceptance: April 23th, 2012
Camera ready papers: May 28th, 2012
19th Annual Electronic Design Process Symposium
Monterey Beach Hotel, Monterey, CA April 5 & 6, 2012
IEEE Computer Society of Silicon Valley (CS-SCV)
Design Automation Technical Committee (DATC)
Council on Electronic Design Automation (CEDA)
The Electronic Design Processes Symposium (EDPS) provides a forum for a cross-section of the top thinkers, movers and shakers who focus on how chips and systems are designed to discuss state-of-the-art electronic design processes and CAD methodologies. The workshop focuses on the improvement of the overall design process, rather than on the functions of the individual tools themselves.
Session Themes suggested:
• Parallel EDA
• High-Level Design - including Requirements-Driven Design Flows
• Cloud Computing - including Software as a Service
• Low-Power Design - with Solution Mapping to 2009 ITRS Roadmap
• 3D IC’s
Authors should submit full-length, original and unpublished papers along with author contact information. Proposals for special, poster, and panel sessions may also be submitted; a 1-page description along with organizer contact information is required. Send papers and proposals to: email@example.com.
Jim Hogan Managing Partner, Vista Ventures
Misha Burich Senior VP, Altera R&D
Feb. 29 Submission Deadline
Mar. 16 Acceptance Notification
Mar. 30 Camera Ready Copy
Apr. 5, 6 On-site RegistrationBrian Bailey
– keeping you covered
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