The countdown begins: On Wednesday next at DesignCon 2012 I’ll be moderating a panel comprising four of the sharpest minds in the electronics industry as they explore the cutting edge of technology and what it means for you, the test engineer.
It’s important to note at this point that this panel is a new addition to DesignCon, and its primary purpose is to be an interactive forum for you, the designer or test engineer, to hear first hand where the experts believe technology is going and what it means for you. The key is interactivity. Ask questions and voice you own concerns, that’s why they’re doing this and depending upon your receptivity, we plan to make it an annual event.
If you can’t attend the conference or the panel, “Delivering on Time-to-Answer: Meeting Designers Needs in Test & Measurement” (ChipHead Theater, Wednesday, 3.45 to 5.00 pm), pose your question below (or email me directly at firstname.lastname@example.org) and I’ll add it to the list. If you want to videotape your question, send it along to me via Dropsend or DropBox and I’ll play it ‘live’ at the event.
So, roll the drums: Who are these minds of which I speak? Well, Greg Peters is vice president and general manager of Agilent’s Component Test Division, Dr. Kevin J. Ilcisin is vice president, and chief technology officer for Tektronix, David C. Graef is vice president and chief technology officer for LeCroy and Eric Starkloff is the vice president of Systems Platforms at National Instruments.
It doesn’t get much better than this, but again, keep in mind, it’s really not about them (don’t tell them I said that). It’s about you, and helping you map out your test strategies.
Indeed, the timing couldn’t be better either: Designers continue to face ever-shorter time-to-market windows and consistently look to their test equipment and for faster ‘time to answer’. Yet this requirement clearly flies in the face of the increasing complexity as designers deal with higher integration, multiple RF interfaces, multiple high-speed serial or parallel signaling protocols, multiple processors and a matrix of IC, board, and system-level interactions and dependencies so fractal in nature that they frustrate even the most experienced test engineers and system designers.
So, join us as we discuss the nature of test, the interactions and issues designers face, how test technology is evolving to meet designers' needs and what lies ahead that you need to anticipate—now.
Again, add your own questions below, or email them to me (video too) so we can make the most of this unique opportunity.
See you next week!