DesignCon 2012 of this next weekend Santa Clara, CA and the technical sessions include something for everyone. The RF/Microwave Techniques for Signal Integrity track has a range of useful sessions, including “The Relationship Between Discrete Frequency S-parameters and Continuous Frequency Responses—Things You’d Better Know When Using S-parameters” (session #14-WP5) explores the relationship between discrete-frequency responses connected with s-parameters and the implied continuous time response. Insights gained from studying this topic in both the frequency and time domains will help identify the conditions for correct sampling and point out the side-effects of the invariable practical conditions when these side-effects cannot be completely dispelled.
In “Fast and Optimal Algorithms for enforcing reciprocity, passivity and causality in S-parameters” (session #14-WP6), you'll discover methods to ensure that errors in your s-parameters do not compromise the effectiveness of your simulation.
If you need to find out the basics of S-parameters, attend “S-parameter Modeling and Simulation for Signal Integrity Analysis” (session #2-MP2), a three-part tutorial session that covers it all. Start out with the fundamentals in “S-parameter Modeling,” which includes modeling considerations for applying S-parameters in system-level simulations; how to use s-parameters in time- and frequency-domain circuit simulations; comparison of S parameters with transmission line models or x-parameters; and measurement and simulation challenges presented by causality, passivity, and bandwidth. Part two, “SPICE Simulation with Frequency Domain Models,” will demonstrate composite channel modeling with s-parameter data; how to handle interpolation and exterpolation; efficient EM solver data formats for SPICE simulation; in special cases such as nonlinear I/O modeling, to name just a few. Part three, “Channel Eye Diagram Generation,” will cover the topic ranging from time-domain simulation setups for SPICE to multi-edge StatEye techniques for highly nonlinear I/O buffers.
Combining digital and analog electronics is as much art as science. Find out what you need to know in the Analog and Mixed-Signal Design and Verification track. Are you performing synchronization or frequency synthesis using a phase-locked loop with a high-Q controlled oscillator (CXO)? Discover the pros and cons of high-stability digitally-controlled oscillators (DCXOs) compared to varactor-based and PLL-based voltage-controlled CXOs in “Analysis of High-Stability Controlled Oscillators for Low-Bandwidth PLLs” (session #2-TA3). You'll also learn about the impact of quantization effects, update delay, and loop filter implementation on the loop performance.
This is just a quick snapshot. Other tracks include:
Chip-Level Design for Signal/Power Integrity
Analog and Mixed-Signal Design and Verification
FPGA Design and Debug
Memory and Parallel Interface Design
High-Speed Serial Design
High-Speed Timing, Jitter and Noise Analysis
High-Speed Signal Processing, Equalization and Coding
Power Integrity and Power Distribution Network Design
Electromagnetic Compatibility and Interference
Test and Measurement Methodology
Follow the links to read abstracts and use the scheduling tool to plan your week.