Breker Verification Systems is attempting to define a new market and they think they have a solution to the problem...
Editor's Note: This morning, I received a press release about a company attempting to break in by addressing a new market – that of SoC verification. The body of the release actually tries to explain the problem and their approach to solving it and does so in a way that I thought it would make a great opinion piece – so here it is:
Breker Verification Systems is privately held and headquartered in the Silicon Valley. Founded in 2003, it has 15 employees worldwide with technical, R&D and business development expertise.
SoC functional verification is a big and complex task with many stakeholders and a variety of objectives and challenges. Using traditional methods, SoC verification engineers are forced to manually develop tests only able to address the tip of the verification "iceberg." Consequently, there is a huge risk of missing system functional and performance problems that will not manifest themselves until first silicon, resulting in delayed time to market and impacting revenue.
Existing block-level testbench-based verification approaches break down for SoC designs containing embedded processors. SoC verification requires automated self-verifying C test cases running on embedded processors. These test cases must exercise a wide range of functional scenarios to ensure that the SoC can support the necessary concurrency, system-level and software functionality while meeting performance requirements.
The SoC verification problem is so daunting that it will only be solved through automation. Complex SoC use cases that cross multiple concurrent applications with shared resources and on-board power and clocking management systems present an overwhelming number of possible scenarios. Automation software is required to assess what to test and to rapidly develop tests needed to adequately cover the wide spectrum of verification objectives.
SOLVING THE SoC VERIFICATION PROBLEM:
Breker Verification Systems’ TrekSoC™ is the first commercially available software that automates the creation of portable self-checking tests for multi-threaded SoC devices. Modular, extensible and scalable, TrekSoc utilizes SoC Scenario Models™ that focus on a device’s intended outcomes and then automatically generates the stimulus required to generate those outcomes.
Unlike transactional testbenches, hand-written embedded-processor tests or other products, TrekSoC combines an intuitive format for describing functionality with powerful engines that generate self-verifying C test cases to verify the specified functionality in existing verification environments. It is used for generating constrained random C test cases to target system interactions that are self-checking and optimized to run efficiently in simulation.
A structured approach to SoC verification, it can be deployed incrementally with a high return on investment. Easy to use and learn, TrekSoC offers simple graph-based models with visualization and coverage analysis, along with easy reuse of verification models. Meant for functional verification engineers and managers who need to verify SoC designs containing one or more embedded processors, TrekSoC is an automatic generator of self-verifying embedded-processor C test cases that verifies top-level SoC functionality.
An SoC Scenario Modeling approach to functional verification handles IP-to-SoC reuse and pre-silicon to post-silicon reuse. The technology provides simple “algebra” to describe a desired verification search space as visualized, using a combination of graphs and graph constraints. It generates input stimulus, checks results and measures coverage closure, creating transactional tests at the IP level and C tests at the SoC level. Visual analytical capabilities include interactive rendering of pre-simulation reachability analysis and post-simulation coverage results.
The TrekSoc verification environment can leverage the existing verification infrastructure. It integrates with all verification methodologies, including UVM, Open Verification Methodology (OVM) and the Verification Methodology Manual (VMM) and hardware language such as SystemVerilog and Verilog and all commercially available simulators. Disclosure: I have performed work in the past for Breker Verification Systems and was compensated for that work. I hope to do work for them in the future as well. I was not paid in any way to place or promote this material.
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