This is a roundup of news or activities in the past few days that may be of interest to people.
Synopsys has announced availability of DesignWare® Embedded Memory and Logic Library IP for TSMC's 28-nanometer (nm) high-performance (HP) and high-performance for mobile (HPM) process technologies. The Synopsys DesignWare Embedded Memories and Logic Libraries are designed to deliver high performance with low leakage and active power, giving engineers the ability to optimize their entire system-on-chip (SoC) design for speed and energy efficiency. This balance is especially critical in mobile applications. In combination with the embedded test and repair technology of the DesignWare STAR Memory System®, Synopsys' embedded memories and standard cell libraries offer designers an IP solution for creating high-performance, low-power 28-nm SoCs with reduced test and manufacturing costs.
Magma Design Automation and MunEDA have announced the completion of a collaborative effort to integrate Magma’s FineSim™ SPICE simulator and MunEDA’s WiCkeD™ tools suite. They claim that the joint solution will enhance and speed the analysis, modeling and optimization of full-custom analog and digital circuit designs – especially in leading-edge 28-nanometer (nm) and 20-nm process technologies. Mutual customers now can invoke Magma’s FineSim SPICE from within MunEDA’s WiCkeD. WiCkeD is a software tool suite for circuit sizing, modeling, optimization, analysis and verification. Its main application areas are analog/RF and full-custom digital designs, IP libraries, standard cell libraries, high-speed I/O, FPGA and memory designs. FineSim SPICE is a SPICE-level simulation analysis tool that incorporates transistor-level simulation analysis capabilities for mixed-signal and analog designs. The new solution, available now, is already in active use by leading semiconductor customers of Magma and MunEDA worldwide.
Gradspring, an online job board featuring entry-level positions for recent graduates, is teaming up with leading global electronic design innovators Cadence® Design Systems, Inc. to bring entry-level engineering positions from around the world to a growing audience of ready applicants. Gradspring provides a service to the human resource community, enabling recruiters to post jobs, identify potential candidates and participate in a community of active, motivated entry-level job seekers. Gradspring enhances career opportunities by providing convenient, organized and affordable access to a job board rich with diverse and legitimate entry-level job openings. For more information about Gradspring, visit www.Gradspring.com.
Analog Devices has announced the release of a new version of its ADIsimRF™ design tool. ADIsimRF design tool is the software accompaniment to their portfolio of RF-to-digital functional blocks, allowing engineers to model RF signal chains using devices from across ADI’s RF IC and data converter portfolio. ADIsimRF Version 1.6 adds support for 29 new RF ICs and data converters as well as functional enhancements. The ADIsimRF design tool provides calculations for the most important parameters within an RF signal chain, including cascaded gain, noise figure, IP3, P1dB, and total power consumption. The ADIsimRF tool also contains embedded data from many of ADI’s RF ICs and data converters, which designers can easily access using pull-down menus. Device tables assist in component selection.
Download ADIsimRF design tool: http://www.analog.com/adisimrf
Austriamicrosystems business unit Full Service Foundry has announced the availability of a new analog/mixed signal high performance process design kit ("HIT-Kit") for its 0.35µm CMOS, High-Voltage CMOS and SiGe-BiCMOS specialty technologies. Based on Cadence Virtuoso Custom IC technology, the new HIT-Kit significantly improves the time-to-market for highly competitive products in the analog intensive mixed signal arena. Supporting designers in creating their first-time-right mixed signal designs even for complex designs, this comprehensive design environment with its highly accurate simulation models and flexible SKILL-based PCells provides a proven route to silicon.
Synopsys and Arteris have announced a collaboration that enables models of Arteris' FlexNoC interconnect IP to be used with Synopsys' Platform Architect environment, offering system designers the ability to simulate realistic system-level performance of their end product architectures. SystemC transaction-level models (TLMs) generated by Arteris' FlexNoC configuration tool can now be easily united with Synopsys' architecture design models and traffic generators, enabling early analysis of end-application performance, and highly efficient optimization of multicore system architectures months before system software or register transistor language (RTL) designs are available.
Brian Bailey – keeping you covered
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