Today’s SoC verification environments require a reusable verification IP (VIP) infrastructure that allows plug-and-play of verification IP in SoC integration. The VIP must include hooks in the verification IP that would make writing an SoC integration test environment (tests, BFMs, monitors, checkers) easier and faster. Typically, SoC verification methodologies focus on verifying only the glue logic of the reused IP, rather than verifying IP functionality in the SoC environment.
The current verification IP landscape comprises multiple implementation languages: C, C++, SystemC, VHDL, Verilog, SystemVerilog, ‘e’, OpenVera, etc. Although SystemVerilog is the unifying standard, legacy use of other languages lingers as IP vendors adopt SystemVerilog. Every VIP brings unique challenges to integration with the SoC environment, such as synchronizing SystemVerilog test sequences with SystemC/C/C++ code. The solution is often VIP specific and takes significant effort to implement. Moreover, because SoC verification environments need to stitch all the heterogeneous VIPs together, which is often a painful process, maintaining the SoC environment is resource intensive as well.
VIP quality also remains a challenge. VIPs come from a variety of sources with varied levels of sophistication. Whether the VIPs are developed externally (purchased) or internally (from a previous project, for example), they often have different interfaces, different methodology supports (OVM, VMM, eRM, UVM) that contribute to considerable SoC integration issues. Many teams have broken down their SoC integration process into several phases solely to detect and fix VIP integration issues as early as possible.
The key question is, “Do we accept this reality of SoC verification, or drive the industry toward a new approach?”
Integrating all the VIP in a SoC environment so that there is a uniform view of validation closure is an effort-intensive process. Ideally, all VIPs would be built on the same toolsets/flows to enable plug-and-play SoC integration. For the last few years, the problem has been made worse with somewhat disparate methodologies, such as OVM and VMM. However, with the Accellera UVM standardization effort, VIPs are converging in the right direction. With the rush to UVM, most EDA vendors are claiming native support of UVM, but if we dive deeper into the VIPs, they still consist of wrapper code around the native C/C++, ‘e’, or Vera. The wrapping layer is a good first step for UVM adoption, but it fails to provide the performance, source-code debugging and other benefits of native UVM implementation. What the industry needs is VIPs written entirely in SystemVerilog with indigenous support for UVM – i.e., no wrapping layers.
With no standard on reviewing VIP capability vs. requirements and no industry-wide agreement on how to score a VIP for a set of given reuse requirements, a standard on packaging VIPs for delivery is needed. There are vendor-specific extensions based on IP-XACT, but they lack comprehensive packaging guidelines for verification requirements (register descriptions, emulation, FPGA portability, etc.). Such guidelines need to be accompanied by an industry-wide set of metrics to score a given VIP.
Verification IP has made great strides in the last 10 years. Nevertheless, the SoC integration challenges require new advances in VIP technology. A new approach to engineering VIPs that fully leverage industry standards will enable development of VIPs tuned for better performance, quality, usability, and better integration.
Dhruba Kalita is a Principal Engineer at Intel. Dhrubajyoti Kalita received a B.E. (Hons) degree in electrical and electronics engineering, and a M.E. degree in Electronics and Control Engineering, both from Birla Institute of Technology and Science, Pilani, India in 1994 and 1997, respectively. He received a Ph.D. degree in Electrical Engineering from the University of Michigan, Ann Arbor, in 2001. The current focus of his work is SoC validation.
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