VIP architectures have evolved over time and this has led to inefficiencies. Synopsys goes back to the drawing board and "all SystemVerilog" VIP emerges...
A couple of days ago, I spoke to Michael Sanie and Neill Mullinger from Synopsys about the release of their new Verification IP (VIP) strategy. The subtitle of their presentation was Next-Generation VIP for Faster SOC Verification. Now I know when I was in the verification business myself, the question I always hated more than anything else was – how much faster? The problem is – as they say – your mileage may vary. There is no specific answer that can be given that will apply to everyone. Of course they tried to squirm out of it, and I kept coming back to it. But first, let’s talk about what is new and different.
History can create problems as well as create opportunities. We have been through a number of verification languages such as e and Vera. A lot of VIP was written in C, even though this was never a real verification language. Then along came SystemVerilog and it was important for the existing VIP to be used in this environment, so wrappers were created. Then we had the first generation of methodologies, such as VMM and OVM and in many cases an extra layer was required. Then came UVM and another set of interfaces/wrapper had to get created. All of this resulted in several wrappers, API and other things getting in the way. In addition, the things that VIP are needed for has been changing in terms of complexity. The protocols that existed ten years ago were very simple in comparison to the protocols in use today. This means that many of the needs of the verification engineer has changed.
So Synopsys decided to go back to the drawing board and recreate the way in which VIP is created from the ground up. They decided that the right path was for the VIP to be 100% implemented in SystemVerilog that would execute natively within UVM, VMM or OVM. They made the way in which sequences and coverage were defined consistent. They built in the test plans and configuration tools, and as a result they claim 2-4X faster performance.
So back to the speedup question. I asked how big an impact this would be for a typical team? They had stated at the beginning of the presentation that a 10X productivity boost was needed, and so VIP performance can only be a part of this. They said that when verifying at the block level, the testbench can be a significant part of the total execution time and the figures they gave me were 30 to 35% of the time in a typical case. So a 4X performance improvement in the VIP could be quite significant.
Time could also be saved in the configuration, verification planning and getting the right coverage models in place.
Perhaps the biggest impact though may come from the debugging side of things. Each new VIP comes with a protocol aware debugger and for protocols that have multiple transactions in-flight at the same time, just seeing a transaction-level view of the traffic may not be enough. This could really help to see what is happening with traffic flow through the system. Today, this protocol analyzer is a post processor, but they have plans to make this interactive in the near future.
The VIP sporting this new structure includes the AMBA, MIPI, HDMI,I2C and Ethernet protocols today and the rest will be rewritten in the future.Brian Bailey
– keeping you covered
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