This is a roundup of news or activities in the past few days that may be of interest to people.
Agilent Technologies has announced that Accelicon Technologies’ software solutions and technology for device-level modeling and validation in the electronics industry are now part of Agilent. The two companies had announced an acquisition agreement on Dec. 1, 2011. Financial details were not disclosed. Accurate, verified device models are critical to reduce R&D design cycles as higher frequencies, smaller technology nodes, new materials and device layouts call for more accurate process design kits. As part of the Software and Modular Solutions Division, Agilent EEsof continues to integrate its industry-leading design simulation with real measurements to improve design efficiency for engineers who develop communications systems. These improved tools and processes solve the increasing complexities they face when designing communications systems for aerospace/defense and commercial wireless applications.
Agilent’s newly acquired solutions from Accelicon include MBP for device-level extraction and model generation, MQA for device-level model validation and AMA for advanced model analysis, including layout effects.
The Accellera Systems Initiative™ announced today that the IEEE Standards Association (IEEE-SA) now offers the latest version of the IEEE 1666™ "Standard SystemC Language Reference Manual," for download at no charge, as part of the IEEE Get program. Announced by the IEEE-SA in November 2011, the revised version of the IEEE 1666 specifies the SystemC™ standard, a high-level design language used in the design and development of electronic systems. The new version encompasses many enhancements, notably support for Transaction-Level Modeling (TLM), a critical approach to enable high level and more efficient design of complex ICs and SoCs. Beginning immediately, companies, universities, research institutions, and individuals worldwide can freely access the standard and develop applications for SystemC-based tools and technologies. To download a copy, please visit http://standards.ieee.org/about/get/index.html#get1666.
ARM has announced the availability of the ARMCortex-A9 MPCore Processor Optimization Pack (POP) for GLOBALFOUNDRIES' 28nm-SLP High-K Metal Gate process technology. Optimized for mobile, networking and enterprise applications, the energy-efficient ARM POP 28nm-SLP for Cortex-A9 processors delivers a performance range from 1GHz to 1.6GHz for worst case conditions, with up to 2GHz in typical conditions. This provides a wide range of flexibility for System-on-Chip (SoC) designers to optimize performance and energy-efficiency using the ARM Artisan Physical IP Platform and Cortex-A9 POP.
Brite Semiconductor (Shanghai) and ARM jointly announced the first tape out of a dual-core ARM® Cortex™-A9 MPCore™ test chip using SMIC's 40nm low leakage process technology. The test chip is an implementation of a dual-core Cortex-A9 processor designed using SMIC's 40nm low leakage process technology. The processor incorporates a 32K I-Cache and 32K D-Cache, 128 TLB entries, NEON™ technology, as well as debug and trace technology from the CoreSight™ Design Kit. In addition to high-speed standard cell libraries, high-speed customized memories and cells were adopted in the test chip to enhance performance. The test chip was signed off at 900MHz (WC), with typical silicon results expected to top 1.0GHz when the results become available in Q2 2012.
SpringSoft and Synopsys have linked SpringSoft's Verdi Automated Debug System with Synopsys' Protocol Analyzer. Part of the Synopsys Discovery™ VIP family, Protocol Analyzer enables engineers to quickly understand, identify and debug protocols in their designs. Through this linkage, the identified protocol violations and errors are seamlessly passed to the Verdi environment for detailed signal-level analysis to rapidly pinpoint the root causes of violations. As leading system-on-chip (SoC) designs incorporate multiple complex protocols, verification IP (VIP) has become a critical component of the verification environment, enabling engineers to reach their coverage goals within tight project schedules. With the increase in protocol complexity, protocol debug is now one of the most difficult and time-consuming aspects of SoC functional verification. This collaboration, implemented with SpringSoft's VIA (Verdi Interoperability Apps) platform, directly addresses these challenges by combining the protocol-centric debug capabilities in Protocol Analyzer with the advanced design debug capabilities of the Verdi system.
Posedge has expanded its NAND Flash Controller IP portfolio by announcing the availability of NVM Express compliant Flash Controller IP Core. While Flash-memory-based solid-state disks (SSDs) provide faster random access and data transfer rates than mechanical drives, typically the host interface to SSDs remains a performance bottleneck. An emerging standard called NVMe (Non-Volatile Memory express), promises to solve the interface bottleneck. Posedge's NVM Express defines an optimized register interface; command set that is scalable for the future and avoids burdening the device with legacy support requirements while sustaining performance in PCIe SSD applications.
Brian Bailey – keeping you covered
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