This is a roundup of news or activities in the past few days that may be of interest to people.
Analog Devices will conduct three webcasts on popular RF topics. A two part series, “Fundamentals of Frequency Synthesis Using PLLs and DDS” will air on March 7 and April 12, 2012 at 12 pm EST and attendees must register for each session individually. Sponsored by Richardson RFPD, “Using Highly Integrated RF ICs to Optimize Your Infrastructure and Point to Point Radio Designs” will be presented on March 28, 2012 at 11 am. This webinar will feature modulators, demodulators, data converters and PLLs.
Register for Fundamentals of Frequency Synthesis, Part I: PLL webcast, March 7, 2012 at 12 pm EST
Register for Fundamentals of Frequency Synthesis, Part II: DDS, April 12, 2012 at 12 pm EST
Register for Using Highly Integrated RF ICs to Optimize Your Infrastructure and Point to Point Designs, March 28, 2012 at 11 am EST
Mentor Graphics has announced with Samsung Electronics that they have successfully delivered a complete design-for-manufacturing (DFM) sign-off reference solution for Samsung’s foundry customers based on the Calibre platform. The DFM sign-off solution is available for consumer and telecommunications designs targeting advanced process nodes. Samsung has already released the Calibre kits to their customers for 32 nm and 28 nm, and has completed evaluation for 20 nm.
Synopsys and Arteris have announced their joint analog and digital IP solutions to implement the MIPI Alliance Low Latency Interface (LLI) 1.0 specification. The combined offerings deliver high performance with low power consumption in a compact silicon footprint while providing interoperability with the MIPI standard. By providing a collaborative solution that adheres to the LLI specification, Arteris and Synopsys give system-on-chip (SoC) designers access to pre-tested and pre-optimized analog and digital MIPI-based IP that can reduce design cost and accelerate time to market.
Synopsys has also announced the availability of a new DesignWare® MIPI M-PHY IP solution supporting multiple speed gears and a broad range of high-speed interfaces for mobile applications. The MIPI M-PHY IP is a 28-nanometer (nm) multi-gear solution that supports six different inter-chip interconnect protocols including the JEDEC Universal Flash Storage (UFS), the USB SuperSpeed Inter-Chip (SSIC), and the MIPI Alliance's Low Latency Interface (LLI), DigRF v4 and future CSI-3 and DSI-2 interfaces.
Synopsys will host a PrimeTime analysis suite Special Interest Group (SIG) event co-sponsored by GLOBALFOUNDRIES, Inc., during DATE 2012 in Dresden, Germany. During the event Synopsys will unveil their latest in Gigascale Design Signoff with Advanced OCV, ECO Guidance and HyperScale Technologies. Speakers include timing experts from ARM, GLOBALFOUNDRIES, STMicroelectronics and Synopsys.
To register to attend this event, or for additional information, please visit: http://www.synopsys.com/cgi-bin/ptsig12/reg1.cgi
March 13th 11:45- 13:30 and lunch is provided.
Cadence has a new release of its Encounter RTL-to-GDSII flow for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers. Developed in close collaboration with leading IP and foundry partners and customers, the new RTL-to-GDSII design, implementation and signoff flow enables more efficient development of SoCs, meeting and exceeding the power, performance and area demands of today's market requirements.
The new Encounter 20-nanometer methodology delivers double-patterning support, the new GigaOpt engine, which integrates physical-aware synthesis technology with physical optimization and GigaFlex technology, a new capability that expands the capacity to handle today's largest designs of 100 million instances or more.
Atrenta has announced that 10 intellectual property (IP) providers have qualified their soft IP for inclusion in the TSMC 9000 IP library using the Atrenta IP Handoff Kit. Those companies, part of TSMC’s Soft-IP Alliance Program, include Arteris, Inc.; CEVA; Chips&Media, Inc.; Digital Media Professionals Inc. (DMP); Imagination Technologies; Intrinsic-ID; MIPS Technologies, Inc.; Sonics, Inc.; Tensilica, Inc.; and Vivante Corporation. The participating companies are able to provide quantitative information to TSMC’s customers regarding the robustness and completeness of their soft or synthesizable semiconductor IP that is part of the TSMC 9000 IP library.
In May 2011, TSMC and Atrenta announced the Soft-IP Alliance Program, which uses Atrenta’s SpyGlass® platform and a targeted subset of its GuideWare reference methodology to implement TSMC’s IP quality assessment program. TSMC requires all soft IP providers to reach a minimum level of completeness, as documented by Atrenta DashBoard and DataSheet reports, before their IP is listed on TSMC online.
Sigrity has been awarded U.S. Patent No. 8,080,897 for the company’s automated optimal sense location capability. This technology pinpoints the best possible position to place a remote voltage regulator module (VRM) sense line on a printed circuit board or package. This single design optimization can increase the ability to meet target voltage thresholds and significantly improve overall voltage margin efficiency by 10-to-30 percent compared to seemingly reasonable alternative locations. The automated optimal sense location capability is implemented in Sigrity’s electrical and thermal simulation tool – PowerDC.
GLOBALFOUNDRIES has announced it has agreed to terms with AMD to acquire the remaining stake in GLOBALFOUNDRIES, fulfilling the company’s long-term vision of becoming an independent foundry company. The agreement, part of an amendment to the commercial Wafer Supply Agreement (WSA) with AMD, positions GLOBALFOUNDRIES as a pure-play, semiconductor foundry company with AMD as one of its primary and strategic customers. GLOBALFOUNDRIES will now be wholly owned by the Advanced Technology Investment Company (ATIC).
ARM has released the latest edition of the ARM Development Studio 5 (DS-5™ v5.9) toolchain with additional support for graphics analysis on ARM Mali Graphics Processing Units (GPUs). The toolchain can be downloaded by developers, enabling them to achieve integrated optimization across the whole system, including both the applications processor and GPU. The ARM DS-5 v5.9 toolchain provides significant benefits to semiconductor suppliers and OEMs, as well as mobile application and game developers, by enabling improved system visibility and decreased time-to-market. In particular, the ARM Streamline™ Performance Analyzer, within the DS-5 toolchain, allows developers to design more interactive interfaces and immersive game play for end users whilst extending battery life. This will enable next generation user experiences for use on smartphones, tablets, smart-TVs and set-top boxes.
Mentor Graphics has released a new version of the PADS® product suite. New features include the ability to associate nets necessary for DDRx interconnect design. Multiple nets can now be “grouped” and given unique high-speed constraints, including length and differential pair rules. Associated nets adhere to these rules during interactive and automatic routing, assuring that tight, high-speed performance specifications are met. Another feature allows a trace to “hug” an existing obstacle like another trace or board outline. This feature will reduce routing time and more effectively use board space. Drafting operations have also been enhanced with new 2D line styles and snap capabilities.
CEVA has announced the availability of its low energy CEVA-Bluetooth 4.0 IP, for both single mode and dual mode applications. CEVA-Bluetooth 4.0 incorporates Bluetooth Low Energy (BLE) functionality, significantly expanding the addressable market for Bluetooth connectivity to include a wide range of smaller, cost-efficient applications previously limited by the power consumption of older Bluetooth standards. CEVA-Bluetooth 4.0 is available both as Single Mode IP (CEVA-Bluetooth 4.0.SM) and Dual Mode IP (CEVA-Bluetooth 4.0.DM).
Brian Bailey – keeping you covered
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