The wholly unrealistic IC development schedule nobody dares openly question is often much worse than I described in my last blog posting.
Last month on these pages I discussed "The elephant in the corner"–the wholly unrealistic IC development schedule nobody dares openly question. In truth, the situation is often much worse than I described. Usually it isn't just one elephant in the corner, there's a herd—a portfolio of projects. In fact, one of the most insidious problems of portfolio management is the failure to adequately verify that project plans are realistic. Because most R&D organizations lack a reliable verification capability, most portfolios end up in chaos—indeed, "the best laid (portfolio) plans of mice and men often go awry."
With that in mind, how many chip design projects is your R&D organization currently working on? If it's a handful or more, my guess is that many will miss schedule—too many projects, too few engineers. When projects are understaffed, the implicit assumption is R&D teams will compensate by achieving enormously high productivity. It doesn't happen. Instead, much of the portfolio slips schedule—often by a lot.
Oversubscription by more than 40 percent is common in the semiconductor industry. That means R&D organizations needs at least 40 percent more engineers to meet the portfolio's time-to-market objectives.
Perhaps it's an open and shut case of wanting to "have one's cake and eat it, too." There simply aren't enough engineering resources to handle all the business opportunities marketing and senior management pursue. But that inconvenient fact rarely prevents major over-commitments. Instead, most projects simply end up underfunded. "Book the business now, and we'll worry about on-time delivery later," seems to be the common refrain in the industry.
R&D organizations can offset portfolio under-resourcing in a number of ways:
(a) reduce the scope of projects—difficult to do because markets and customers demand maximum functionality & performance, and likewise, competitors are constantly upping the features/performance ante; (b) re-sequence the portfolio's execution pipeline by delaying certain projects' start dates ("resource leveling")—it's done sometimes but typically not enough to have much impact; (c) "encourage" the R&D organization to work longer hours, which increases engineering throughput—it happens quite a bit, but engineers burn out and productivity often declines; (d) the R&D organization can attempt to boost its productivity; unfortunately, productivity often must increase far more than humanly possible within the target time horizon, because chip design complexity is increasing faster than productivity typically improves.
So what's the solution? First, organizations must be far more discriminating in selecting business opportunities and projects. That puts the onus on marketing organizations, as well as senior management, to gain greater insight into the markets they serve. To this end, marketing should establish a robust process for quantifying the likelihood of achieving its forecasted revenues—assuming R&D meets its commit dates—and it should present those (realistic) probabilities to senior management. Second, productivity implied in project plans must be measured at the outset of each project, and projects assuming unrealistic performance should be flagged. Implementing this strategy leads to streamlined portfolios whose projects meet schedule and revenue targets. Moreover, both the engineering and marketing organizations become more accountable for meeting schedules and forecasts.
Ronald Collett is president & CEO of Numetrics Management Systems Inc.