Duolog, Mentor, ClioSoft, Carbon, Arteris, EdXact, Methodics, ARM, Freescale, Fujitsu, Vivante made the lineup today. See here for their news...
This is a roundup of news or activities in the past few days that may be of interest to people.
Duolog Technologies and OCP-IP have jointly announced that Duolog’s OCP toolkit is now available for evaluation in the cloud on the Xuropa Cloud Platform. OCP Conductor and Tracker join Socrates Bitwise, Weaver and Spinner in the Socrates Lab on Xuropa. Users with a web browser can test-drive Duolog’s System-on-Chip integration tools in minutes. To access Duolog’s freely available OCP toolkit and also the Socrates integration applications, visit the Socrates Lab on Xuropa. Once engineers have utilized the OCP toolkit, they can then request a free members’ copy via the OCP-IP website.
Mentor Graphics announced that a new flow developed for GLOBALFOUNDRIES by the Mentor® Consulting Division (MCD) using the Calibre® suite of tools has demonstrated the ability to improve incoming design yield. A silicon experiment performed by GLOBALFOUNDRIES and Mentor resulted in a significant yield increase on a test chip after the integrated flow made automatic design-for-manufacturing (DFM) improvements using multiple Calibre tools for analysis and direct modification to the GDS layout database. The flow, which is available to GLOBALFOUNDRIES customers for 45/40 and 32/28 nm processes, features rapid turnaround time for full-chip designs, maintains design performance specifications, and helps ensure that the results are DRC clean by immediately verifying all changes during the modification process. The flow quickly filters the design database to identify areas that require DFM improvement, to apply needed enhancements, and immediately recheck the modified layout to ensure that the changes do not introduce DRC violations or other issues. The flow employs the Calibre nmDRC, Calibre YieldAnalyzer, and Calibre YieldEnhancer tools to automatically perform metal widening, via doubling, and via enclosure improvements, including support for rectangular vias.
ClioSoft reported a 53% annual increase in bookings for 2011. The rise in bookings was attributed to increased adoption by existing customers as well as the addition of 23 new customers. Growth in all regions was steady, with the highest growth in Europe, which booked a 139% increase over 2010. ClioSoft’s SOS hardware configuration management platform provides management and version control of design data, streamlining the design process by enhancing communication and facilitating efficient and accurate sharing of design data from concept through tape-out. The tight integration of ClioSoft’s design data management suite with major design flows improves hardware design team productivity, reduces the chance of mask re-spins due to configuration errors and makes design reuse more efficient.
Carbon Design Systems and Arteris have announced that they have implemented a partnership agreement that enables accurate models of Arteris NoC interconnect IP to be generated, managed and distributed using the Carbon IP Exchange web portal. The joint Carbon/Arteris solution offers design teams a way to easily create and import accurate Arteris FlexNoC interconnect models for Carbon SoCDesigner Plus.
EdXact announces the availability of Viso™, the companies solution for parasitics analysis. Viso allows designers to carry out parasitics oriented static analyses of designs of any size. The tool is intended to be used for those increasing number of cases, where interconnect related problems turn debug difficult, where there is a need for detailed analysis and where spice simulation, even accelerated, cannot satisfy the tight time constraints of a design and verification team. Typical applications of the tool comprise the analysis of ESD related electrical layout rules, simulation pre-qualification in order to avoid unnecessary spice simulations, verification of electro-migration related design rules, detection of opens and shorts, sufficient via connections, and the validation of the layout of Power MOS transistors.
Methodics has announced its VersIC™ platform is now integrated with the Synopsys Galaxy Custom Designer solution for cell-based and custom IC designs. The integration provides IC designers with a robust design data management foundation to use within the Synopsys custom IC design environment, enabling greater efficiency, predictability and quality in how design data is generated, used and tracked in complex multi-team IC design projects.
ARM has announced the ARM® Cortex™-M0+ processor, their most energy-efficient microprocessor. The Cortex-M0+ processor has been optimized to deliver ultra low-power, low-cost MCUs for intelligent sensors and smart control systems in a broad range of applications including home appliances, white goods, medical monitoring, metering, lighting and power and motor control devices. The 32-bit Cortex-M0+ processor consumes just 9µA/MHz on a low-cost 90nm LP process, around one third of the energy of any 8- or 16-bit processor available today, while delivering significantly higher performance.
Freescale Semiconductor says it will demonstrate its new Kinetis L series microcontrollers (MCUs) built on the ARM® Cortex™-M0+ processor at DESIGN West in San Jose, California. Alpha sampling of Kinetis L series devices will begin in the second quarter of 2012. Freescale's early demonstration of Kinetis L series devices is possible due to the close partnership between Freescale and ARM during the Cortex-M0+ core development process.
Fujitsu Laboratories has developed what they claim to be the world’s fastest simulation technology for systems using the ARM computing core. They claim it is able to faithfully reproduce hardware operations with cycle-for-cycle real-time accuracy. It runs as fast as a JIT compiler, but with precise cycle-level simulations with low system overhead, based on a just-in-time compiler. This makes it possible for a standard PC environment to simulate an ARM multicore system with cycle-level fidelity at speeds greater than 100 MHz. Simulations run with a +/-5% margin of error relative to running on the hardware, for fast, faithful simulations.
Vivante has announced that it has worked with Cadence to qualify the Cadence double data rate (DDR) Memory controller on-chip intellectual property (IP) solution for use with Vivante's graphics processing unit (GPU) IP solution. GPUs are capable of processing massive amounts of data in order to create the most advanced and realistic 3D visual effects on mobile, embedded and home entertainment devices. To render high quality images, the GPU requires access to external DDR DRAM through a highly optimized, low-latency DDR memory controller.
The collaboration between Cadence and Vivante has created a tightly coupled memory subsystem that maximizes the efficiency between the GPU, memory controller and external DDR memory. Vivante's memory-friendly architecture uses innovative design features like burst building, request merging, efficient data access, compression, prefetching, smart banking, prediction and much more.
Brian Bailey – keeping you covered
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