Eeek alors! The net is buzzing with the news that the folks from Altera and TSMC have just announced their joint development of what they describe as “The world’s first heterogeneous 3D IC test vehicle using TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) integration process” (see also Dylan McGrath’s column TSMC, Altera team on 3-D IC test vehicle).
So what is this all about? Well, first of all, CoWoS is an integrated process technology that attaches device silicon chips to a wafer through a chip on wafer (CoW) bonding process. The CoW chip is attached to the substrate (CoW-On-Substrate) to form the final component. By attaching the device silicon to the original thick wafer silicon before it finishes the fabrication process, manufacturing-induced warping is avoided. TSMC plans to offer CoWoS as a turnkey manufacturing service.
On the one hand this is very exciting news – especially the part where they say things like “Heterogeneous 3D ICs are one of the innovations enabling the industry’s move beyond Moore’s Law by stacking various technologies within a single device, including analog, logic and memory.”
One thing to be careful of here is that the current announcement is of a test vehicle – not a final product. Another point is that this test vehicle should really only be classed as a 2.5D IC, because it involves a number of die being attached to a silicon interposer, which is in turn attached to the package substrate using Thru Silicon Via (TSV) technology. A true 3D IC involves die being stacked on top of other die (see also The challenges of 2.5D versus 3D).
Now, you may think that the Altera test vehicle is similar to the Virtex-7 2000T from Xilinx (Click Here
and Click Here
for more details on the Virtex-7 2000T), but there are significant differences (not the least being that the 2000T is already in production). For example, the 2000T currently involves four identical (homogeneous) FPGA die being mounted on the same silicon interposer. By comparison, Altera’s test vehicle is geared up to exploring the possibilities of mounting a bunch of diverse (heterogeneous) die, including FPGA, memory, processors, analog, and optical … all of which has the potential to be very exciting indeed.
Another difference is that the process of mounting the die on the interposer in the Altera-TSMC solution is all performed by TSMC. As the Altera-TSMC release states “TSMC’s integrated CoWoS process provides semiconductor companies developing 3D ICs an end-to-end solution that includes the front-end manufacturing process as well as back-end assembly and test solutions.”
By comparison, although the folks from Xilinx also use TSMC as their foundry to create their FPGA die, these die are subsequently mounted on the interposer by another company. I currently have no data as to how the different approaches affect things like yield and so forth.
The folks from Altera say that their vision for heterogeneous 3D ICs includes developing device derivatives that allow customers to mix and match silicon IP based on their application requirements. Altera will leverage its leadership position in FPGA technology and integrate various technologies with an FPGA, including CPUs, ASICs, ASSPs, memory, and optics. Altera’s 3D ICs will enable customers to differentiate their applications by leveraging the flexibility of the FPGA, while maximizing system performance, minimizing system power and reducing form factor and system cost.
As I say, this is all very exciting – I, for one, cannot wait to see what happens next…
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