The success of NAND flash memory in the semiconductor market is mainly driven by continuous and tremendous growth in the mobile phone and tablet PC markets, and the growth of adoption of high performance solid state drives (SSDs) as a replacement for hard drives in computers. As Intel and Micron jointly announced last year, a NAND flash product with a terabit capacity, comprising a simple stack of several dice, can be realized with the advent of 20-nm manufacturing technology in conjunction with a break-through concept in cell architecture.
During the past years, NAND flash has enjoyed the highest density among the commercial memories due to its excellent physical scalability and multi-level cell (MLC) approach with two or three bits per cell. However, the recent demand spike for NAND flash memories in portable electronics has resulted in a much drastic scaling down of the device structure of NAND to obtain higher density, faster speed and lower bit cost devices. The aggressive scaling of a cell size in NAND flash memory is expected to face severe barriers in sub-20-nm floating gate-based flash cell with conventional architecture.
In response to the challenges mentioned, Intel and Micron’s joint venture for process development, IM Flash Technologies (IMFT), aggressively pursued a NAND cell shrink, and, as a result, has successfully developed and manufactured high density multi-level NAND flash memories with a 20-nm design rule for the first time. IMFT also revealed an innovative memory structure with the introduction of a fully planar floating gate cell design. IMFT, often considered a leader in the NAND flash manufacturing process, has introduced a cell planarization integrating with high-k/metal gate (HKMG) stack that would considerably overcome many of the physical and electrical scaling challenges brought on by moving to the 20-nm node or further beyond.
By introducing the 20-nm process technology in the production of their 64-Gbit MLCNAND flash memory, IMFT establishes itself as the leader in new process node implementation. Measuring in with a die size of just 117 mm2, this NAND device features an area size that is approximately a 30 percent reduction over the IMFT’s existing 25-nm 64-Gbit NAND flash. IMFT’s 64-Gbit NAND flash is fabricated in a single poly, metal gate and triple metal levels and is distributed in a 48-pin lead-free TSOP package. The 64-Gbit of single flash memory die is divided into four banks with one-sided bond pad arrangement and memory area efficiency is 52% which is comparable to previous 25-nm 64-Gbit NAND device having the die size of 162 mm2.
In a conventional NAND floating gate cell, the control gate (CG) and inter-poly dielectric wrap around the floating gate (FG) and coupling factor greatly relies on the floating gate sidewalls as shown in the figure below.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.