Power is a game changer in the EDA industry. Not only is it a new factor that has to be optimized, along with area and performance, but it is also a factor that permeates itself throughout the entire flow from system concept to fabrication technology and from hardware to software. No one group can make a design low power. It takes a concerted effort, and yet anyone one person can destroy the power profile of a design.
Where in the flow can you save the most power? That depends upon who you talk to. Arvind Shanmugavel Director of Applications Engineering Apache Design, Inc. says the Register Transfer Level (RTL) stage is the one in which the most amount of power can be reduced. This is the first stage in the IC design process where designers can make architectural decisions to reduce power and specify the proper power intent. At higher levels of abstraction there is no micro-architecture. Shawn McCloud, VP Marketing at Calypto Design Systems has a slightly different take. He says that for hardware subsystems, the earlier the better. 80% of the power savings opportunity is at RTL or above where the hardware architecture is determined. Venki Venkatesh, Director of Engineering, Atrenta Inc. agrees saying the sooner, the better. At the architecture level and the RTL level, you have the maximum opportunity for power optimization. Another similar vote comes from Ely Tsern, VP and CTO for Rambus’ Semiconductor Business Group who says from the very beginning and throughout the design process. Power drives key architecture, product definition, and design choices across all types of compute devices throughout the design process.
Achim Nohl, Technical Marketing Manager for Virtual Prototyping at Synopsys wants to move up in the flow. He says the earlier low power techniques can be applied to the design, the bigger their effect on overall power consumption. For example, in today’s electronic products, energy efficiency is highly influenced by the software.
What about at the technology level?
In June of last year Samsung said its 28-nm LP process delivers a 35 percent reduction in active and standby power at the same frequency compared to the company's 45-nm LP process and the 28-nm LPH process offers 60 percent of active power reduction at the same frequency over 45nm LP SoC designs. TSMC states that their 28HPL process reduces standby power by more than 40% compared to the 40LP process. GLOBALFOUNDRIES has three power levels for their 28nm node as shown in the figure below.
How much can software really affect power? In the article “Efficient C Code for ARM Devices” written by Chris Shore at ARM he says: an external memory access is typically going to take 100 times longer than accessing cache and cost 50-60 times the energy. That one figure shows how significant the software impact can be.
Other Power Editorials:
If you spot an error, would like to propose an improvement or addition to this entry, or anything within this power archive, please let me know by sending me an email
. Your comments will be added, and your name will be preserved in the document indicating your participation in its improvement.
Go back to the root of the EDA Designline Power Series.