The total power consumed by a chip is the sum of switching or dynamic power and passive or leakage power. In older technologies, the leakage power was insignificant. As devices have been scaled, the gate oxide thickness has decreased and with it an increased probability of tunneling. This is a major component of the leakage current.
The dynamic component of power is due to the capacitive load in a design, CL. This is charged through a PMOS transistor whenever a net makes a transition from 0 to 1. The energy drawn from the power supply is CLVdd2. Half of this is stored in the capacitor, the other half is dissipated in the transistor. For the 1 to 0 transition, no additional energy is drawn from the power supply, but the charge held is dissipated in the NMOS transistor. Assuming the node changes at a frequency f, then dynamic power is fCLVdd2. While there are other forms of dynamic power consumption, they are much smaller and will not be discussed here.
A voltage reduction will have a considerable impact due to the voltage squared term. Unfortunately performance is also related to voltage since the gate drive Vgs Vt is reduced.
Passive power can be defined as I * V, where I is the leakage current. There are five components of leakage currents in CMOS transistors, namely:
- Gate oxide tunneling leakage. Silicon dioxide SiO2 is the typical material used as an insulator, but at very small thickness levels electrons can tunnel across it. This is an exponential relationship such that halving the thickness increases the leakage by a factor of four. This was not an issue until transistors dropped below 130nm. Using high-k dielectrics instead of SiO2 allows similar device performance, but with a thicker gate insulator, reducing this current.
- Subthreshold leakage. Transistors have a gate-source threshold voltage below which the current (called sub threshold current) through the device drops exponentially. As supply voltage has decreased to reduce dynamic power consumption, the threshold voltage has been decreased as well which results in less gate voltage swing below the threshold to turn the device off. Sub threshold conduction varies exponentially with gate voltage.
- Reverse-bias junction leakages. Small leakage currents are caused by the formation of a reverse bias between diffusion regions and wells or between wells and substrate.
- Gate Induced Drain Leakage. This is caused by high electric field effect in the drain junction of MOS transistors and is primarily handled by the physical way in the fabrication technology.
- Gate current due to hot-carrier injection. This is due to drift of the threshold voltage in short channel devices and related to high electric fields created within the device. Again this is controlled primarily in the fabrication technology.
As we see, a tradeoff has been made between the dynamic and static power consumption. The reduction in voltage has reduced the dynamic power but increased the static power.
Other parts of this series include:
Brought to you by Brian Bailey
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