The practical use of such a solution depends more on the quality of RTL it can generate in addition to the power reduction it can achieve...
Power, performance and area (PPA) are undoubtedly the most important factors for any semiconductor chip, irrespective of whether it is used in a mobile or a wired device. Mobile devices need to consume lower power for longer battery life and wired devices for lower system-cooling costs. In the past, traditional EDA tools have mainly focused on optimizing performance and area through various synthesis and layout techniques. Automated solutions for power reduction are seriously being sought now.
The main culprits for large power consumption in deep submicron designs tend to be clock networks, highly active combinational logic, data paths and memories. Broadly, there are three areas that provide the greatest return for power reduction. The first solution is power domain management; nothing saves power like turning things off. Another important strategy from a design perspective is micro architecture optimization. Lastly, the elimination of unnecessary activity for the combinational logic, registers and memories can save significant power. But today, semiconductor designers are at different stages of adoption of low-power design techniques.
The introduction of UPF and CPF formats has clearly shown a way to define the power intent for multi power and voltage domain management, but the effectiveness of these definitions is dependent on the implementation tools’ support for the evolving standards. Power architects and designers in the mobile or microprocessor space also spend a lot of time making micro architectural changes to lower the power consumption. However, there is no mainstream push-button power-reduction solution for reducing activity across the design for combinational logic, registers and memories.
In recent years, many automatic power optimization tools have emerged. These tools create a power-optimized register transfer logic (RTL) design from an existing design written by hand or generated from high-level synthesis (HLS) tools. These tools take in the original RTL and generate a new RTL that is power optimized. Due to time-to-market pressure and lack of low-power expertise within design teams, such push-button solutions are being perceived as highly valuable. Coming from a software development background, I always relate this to the following scenario - what if I feed in 10,000 lines of my carefully written C code to a tool for better code coverage? The output I get is a C file where 1,000 lines of code have been modified. Would this tool-generated C code be acceptable for future reuse and meet the software-coding guidelines? Is a functionally equivalent C code good enough for maintaining software-coding best practices?
We can now realize that the problem for RTL designers in this regard is similar to software developers. A software developer has to worry about readability, preserving comments and naming conventions in the new C code. Similarly, the RTL designer has to worry about preserving the look and feel of the original RTL; maintaining comments, port, instance or bus naming conventions; adhering to synthesizability, simulation, and clock domain crossing requirements along with ensuring minimal impact on timing and routing congestion for the design.
While every last drop of power savings is the need of the hour, the key challenge for the push-button solution is really ensuring that the quality of the automatically modified power-optimized RTL is maintained while meeting the design’s performance and area requirements. The adoption of such a tool in the design flow is clearly a function of the quality of RTL generated, in addition to the power reduction achieved. However, most power-reduction tools focus on the latter part. Ensuring the quality of the RTL needs a much broader gamut of technologies, and is a tougher problem to solve.
The ultimate push-button solution should have built-in knowledge of the design with checks for RTL naming conventions, synthesizability, design for test (DFT), timing and verification requirements. The power-optimized RTL should also ensure that the clock domain crossing guideline is followed to avoid metastability issues. Similarly, the solution should also support last-minute engineering change orders (ECO) during physical implementation and bring in the surgical changes at RTL to maintain the golden source.
In a recent case of one Japanese mobile application chip, it was able to get about 18 percent power reduction using push-button techniques by improving clock gating. However, the designer also looked at the estimated power numbers at RTL and at activity reports from simulation data for different modes of operation. In addition, the designer made micro architectural changes by implementing different voltage and power domains and by splitting large memories into smaller ones to get an additional 20 percent reduction in power. Hence, it was a combination of manual and automated techniques that helped achieve a total 38 percent reduction in power.
Another popular cell phone application processor design team runs daily regressions of power estimations at RTL for every code check-in and correlates the power numbers for the netllist handoff every few weeks. Memory access rates and the efficiency of each clock gating enable are reviewed to make relevant design tradeoffs. Dashboards and trend charts are created for managers to get visibility into the RTL blocks that show significant change in power numbers for change in functionality on a daily basis to avoid last-minute surprises.
So, truly a push-button power-reduction solution is what all designers need. But the practical use of such a solution depends more on the quality of RTL it can generate in addition to the power reduction it can achieve.
The ultimate solution? An automated power-reduction capability along with an accurate RTL power-estimation tool that provides activity charts and enables score cards to help audit the power savings at different stages in the design flow.
Siddharth Guha is a Senior Engineering Manager at Atrenta India. Siddharth holds a bachelor’s degree in engineering from Netaji Subhas Institute of technology (NSIT), Delhi. Siddharth is primarily responsible for SpyGlass Power Estimation, Reduction and SEC products. You can reach him at firstname.lastname@example.org
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