Recently Rick Merritt of EE Times reported on his interview with Mark Bohr, "Mr. Process Technology at Intel," and wrote: "It’s the beginning of the end for the fabless model according to Mark Bohr."
Quite naturally this caused many responses, with the majority of them hinting that Intel is trying to break into the smart mobile space by sowing doubt in the future of the existing ecosystem around TSMC-ARM and multiple fabless vendors.
We recently wrote two very relevant blog entries: Is NVIDIA in a Panic? If so, what about AMD? Other fabless companies? (04/02/2012); and Why Samsung will give Morris Chang sleepless nights (02/05/2012)
With recent reports about Qualcomm having issues with TSMC, Apple not being able to shift out from Samsung (their competitor) to TSMC, AMD having severe issues and trying to shift some of manufacturing from GlobalFoundries to TSMC, and straight out statements such as: "NVIDIA deeply unhappy with TSMC, claims 20nm essentially worthless," as was discussed in EE Times opinion: Required change in EDA vendors’ role and reward vs. scaling yield, one can't avoid the question: Are we facing a dramatic reversal of the trend from the Foundry model back to the IDM model?
It does seem that advanced scaling these days provides a significant advantage to the integrated model, where trade-offs between design, library EDA, and manufacturing, provide a better end product. Such an integration advantage manifests itself with respect to yield, now that the majority of the yield losses are design-related rather than random defects, and to manufacturing cost, as some of the layers needs double or even triple/quad patterning.
Accordingly, this might explain why both TSMC and GlobalFoundries recently announced investment in 3D IC processing lines as reported by EE Times (TSMC plans 3-D IC assembly launch early in 2013; GlobalFoundries installs gear for 20-nm TSVs). As the current scaling trend works against them, they both chose to move the game to a court where an ecosystem would be more powerful than corporate vertical integration.
We at MonolithIC 3D Inc. are very pleased to see 3D ICs becoming a key business strategy, and truly believe that adding monolithic 3D manufacturing capabilities will extend foundries’ strategic benefits even further. Monolithic 3D, with its 10,000x better vertical connectivity, provides an exciting alternative to pure dimensional scaling. Moore's law is about doubling the number of transistors, which could be easily achieved using existing process and lithography by simply doubling the number of layers carrying transistors. Scaling through the third dimension provides power, speed, and cost benefits similar – or even better -- than we once used to get from dimensional scaling (see "Why Monolithic 3D" for more information).
In addition, monolithic 3D provides benefits that cannot be achieved with dimensional scaling such as pulling out embedded memory into another layer on top of the logic. In a typical SoC the embedded memory may represent 50% of the die area and include hundreds of memory macros, requiring too many vertical connections for TSV but is a very simple task for monolithic 3D integration.
A dedicated memory layer also allows optimizing the first layer for logic and the second layer for memory, which could be even a DRAM rather than SRAM, and would need fewer costly metal layers. Another advantage is the realization of logic-cone-level logic redundancy, as described in Monolithic 3D IC Could Increase Circuit Integration by 1,000x and in Redundancy & Repair with Monolithic 3D.
In summary, the current trend in the semiconductor industry indicates that IDMs have a significant advantage in the leading edge dimensional scaling race. Foundries recognize it and are responding by adding 3D capabilities. They could do even better by also adding monolithic 3D.
-- The author Zvi Or-Bach is president & CEO of MonolithIC 3D Inc. Opinions expressed here are solely those of the author.