After one year we see the first results of the transfer of the Catapult technology from Mentor to Calypto. ESL power optimization...
It was almost a year ago (8/26/2011) when Mentor announced that Catapult would become a part of Calypto and today we see the first result of bringing that technology together with the power optimization technologies developed within Calypto.
Power became a first class optimization target some time ago and yet few tools treat it as such. Speed and area have been the primary optimization targets for synthesis at both the RTL and ESL levels. There is good reason for that – it is very hard to accurately estimate power using high-level models and in addition, total energy consumption is vector dependent.
Today, Calypto is announcing their first attempt at low-power synthesis. Catapult Low-Power provides closed loop optimization across power, performance and area (PPA) to address the challenges of power-aware design.
According to Calypto, Catapult LP takes advantage of Calypto’s PowerPro technology by embedding it “under the hood” of Catapult to produce the lowest power RTL and to optimize designs at the architecture level where 80% of power decisions are made. This enables designers to explore different hardware architectures and measure the power, performance and area of each solution. The net result is an ability to perform architectural refinement from an abstract C++ or SystemC model and deliver PPA optimization from high-level synthesis. Catapult LP goes beyond the architecture level by also looking at fine grain clock gating. This two prong approach of optimizing the architecture followed by maximum clock gating efficiency at the register level promises the greatest power savings.
To address my previous remark about power consumption being vector dependent, Catapult LP uses real vector sets for ESL power evaluation. This is compared to others who use statistical evaluations for power. The problem is that this approach does not take into account natural data correlation as would happen in audio or other data streams (See: Power: a significant challenge in EDA design). At the RT level the tool uses fast synthesis to get PPA estimates. They call it an elastic engine that can trade-off between runtime and accuracy. This gets them to within 15% of gate-level results and they claim that this has been good enough for people using it for design purposes.
The accuracy levels for FPGAs have not yet been evaluated and they also have more limited capabilities for things such as clock gating.
Brian Bailey – keeping you covered
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