This entry is the final entry in the what to see at DAC blog series. It includes listing about the demos that companies will be showing in the areas of IP, Flows and methodologies and services etc...
This entry is the final entry in the what to see at DAC blog series. It includes listing about the demos that companies will be showing in the areas of IP, Flows and methodologies and services etc.
Several weeks ago, I asked companies to send me information about the demos that would be showing at DAC this year. I am pleased to say that many companies responded. I hope you find this better than another list of what you must see at DAC, instead, you can be guided by some real information that may actually be helpful in planning your trip around the show floor. Companies that did not get information to me, feel free to add your information by placing a comment on this article.
Previously published are Verification, Above RTL and RTL to GDS II
is addressing the soft IP quality problem with IP Kit. They will be showing their DashBoard and DataSheet reports that tell you about IP completeness and integration risks. They will also be talking about their flow for continuous quality improvement with automated regressions and trend analysis.
Booth # 2230
Shortening IP Integration and Verification Time for SoC Development with Third-Generation Protocol Compliance using the Cadence Verification IP Catalog.
IP Central™ provides close collaboration between project managers, IP owners, chip designers, and verification teams, enabling them to publish and integrate their IP in existing flows. Design teams can use IP Central to identify IP bugs, trace bug dependencies, and get notification of bugs and fixes across all IP versions and designs. IP changes associated with bug fixes can be viewed in the bug tracking system, and the bug history can be viewed in the IP Central repository. IP can be imported or linked from commercial, open source and internal design management systems, then searched for by configurable, dynamic specifications.
Flows, Methodologies and Data Management
will introduce SatinTech MS™, a software solution that allows companies to create an automated monitoring environment for existing design and delivery practices. With SatinTech MS, methodologists and project leads can quickly build multiple checklists to reflect existing design processes, and then designers can run these checklists at any design step, in association with their current log files and other design flow artifacts. Raw design data are turned into actionable information and smart design decisions can be made with fact-based accountability. Extracting and presenting information in real time helps engineers to monitor issues before they impact the bottom line.
Booth # 2210
SOS Design Collaboration platform is a multi-site development environment that enables global team collaboration, design and IP reuse, and efficient management of design data from concept through tape-out.
The company’s hardware configuration (HCM) management solution is integrated into all the major design flows -- Cadence’s Virtuoso® Custom IC, Synopsys’ Galaxy Custom Designer, Mentor’s IC flows, and SpringSoft’s Laker™ Custom Layout Automation System. ClioSoft's Universal DM Adaptor technology "future proofs" data management needs by ensuring that data from any flow can be meaningfully managed. In 2011, the company also introduced Visual Design Diff (VDD) engine that enables designers to easily identify changes between two versions of a schematic or layout by graphically highlighting the differences directly in the editors.
Booth # 2426
IC Manage GDP is a scalable, design management system for SoC, IC and FPGA development teams. GDP provides designers multi-site collaboration across designs and across global teams. Design teams use GDP to find, modify, release and track usage of design data through tapeouts. IC Manage will demo GDP’s unique bug dependency management system that improves the verification process showing how designers can identify bugs, trace bug dependencies, and selectively propagate fixes across all designs.
provides automated design solutions for micro-electromechanical systems (MEMS) and virtual fabrication of MEMS and semiconductor devices.
They will showcase the MEMS+ 3D design suite, a common platform for MEMS+IC design. The MEMS+ platform provides a design and simulation environment with system-level to IC implementation flow. Users can define and control variables and parameters for every aspect of a design, including 3D geometry, physical layout, process technology, materials and behavioral simulation models. It offers seamless integration with algorithmic evaluation tools like MATLAB Simulink from MathWorks and transistor-level tools like the Virtuoso Custom IC design suite from Cadence Design Systems. MEMS+ is also compatible with existing MEMS design methodologies based on solid modeling and finite element analysis.
Views™ storage acceleration software is a version aware, virtual file system that delivers dramatically reduced disk space usage and Zero-Time Sync™ (ZTS) to local and remote sites. IC Manage Views accelerates EDA tools by utilizing local storage for reads, and network storage for writes; designers get reads at near instant local speeds avoiding network storage bottlenecks. A one gigabyte, 10,000 file workspace takes approximately one second to populate, allowing tools to run immediately as IC Manage Views streams data on demand from a local server or remote proxy. Subsequent reads are served from a local cache with automatic quota management.
L-Edit MEMS Designer: Design tools for microelectromechanical systems. Watch how L-Edit combines with high-performance add-ins that include curve tools, DXF import/export and design rule checking (DRC).
MEMS 3D Solid Modeler – a 3D viewing tool – powered by SoftMEMS –creates a 3D view of a MEMS device from a selected layout area and fabrication process description.
Booth # 1126
Verific Design Automation
Industry-standard, IEEE-compliant SystemVerilog and VHDL parsers and elaborators. Verific’s software serves as the front end to a wide range of EDA and FPGA tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. Along with demonstrations in its own booth, Verific's software can be found in at least 20 other exhibitor booths at DAC who use Verific as their RTL front-end.
Provides ASIC/SoC design services, SoC/Super SoC integration and manufacturing services, and high-performance IP to fabless semiconductor companies, system manufacturers, foundries and IDMs. Its Perseus™ design management frame work enables fast delivery and repeatable and consistent design closure on complex chip design projects. By combining design and leading-edge process expertise with manufacturing services and an extensive IP portfolio, Uniquify offers a turnkey solution that spans chip specification and design through volume delivery of packaged and tested parts.
Brian Bailey – keeping you covered
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