Bulk silicon may be nearing the end of the line as scaling becomes more problematic, FD SOI gives it a kick in the pants, possibly down to 11nm...
For decades, we rode the technology wave by building smaller and smaller transistors into a bulk silicon wafer. Around 90nm, we began to realize that there were problems ahead as voltage scaling slowed and leakage currents increased. Small changes were made in the process to lengthen the bulk lifetime, but there are reasons to look at completely different ways to build circuitry, especially at the latest geometries of 28 and 20 nm. Once such possible way forward is Fully Depleted Silicon of Insulator (FD SOI). Researchers believe that this technology will scale down to 11nm.
FD SOI relies on an ultra-thin layer of silicon over a Buried Oxide layer. Transistors built into this top silicon layer are Ultra-Thin body devices and have unique, extremely attractive characteristics according to Soitec, a manufacturer of the wafers needed to build these products. I spoke to Soitec’s Steve Longoria – SVP Business Development, who walked me through some aspects of the technology.
Figure 1 – FD SOI transistor
Looking at figure 1, the wafer starts with a buried oxide layer that may be about 25nm thick. On top of this is a 15nm silicon film with very tight tolerances. Longaria said that the tolerance on this is 5 Angstroms across the wafer. This creates less variability in the production process leading to higher yields. From a physical point of view, the very thin silicon layer enables the silicon under the transistor gate (the body of the transistor) to be fully depleted of charges. The net effect is that the gate can now very tightly control the full volume of the transistor body. That makes it much better behaved than a Bulk CMOS transistor, especially as supply voltage (hence gate voltage) gets lower and transistor dimensions shrink. In addition, FD-SOI does not require doping in the channel. Simulations and early silicon data predict that, at 22nm, 6T SRAM macros built on FD-SOI could reach 6-sigma yield at VDD and as low as 0.5 to 0.6V .
While wafer costs are clearly higher (Soitec estimates about $500 per 300mm wafer in high volumes in 2012 – depending on wafer specifications) the manufacturing costs are cheaper because several manufacturing steps are eliminated. Photo masks may see a reduction from about 47 for bulk down to 32 for FD SOI, implants decrease from 63 down to 15 and the number of processing steps from 328 down to 241 according to IC Knowledge.
ST Ericsson is one company using this substrate for their NovaThor U8540 with an ARM Cortex A9, used in smart phones . They say that using FD SOI translates to 4 more hours of high-speed browsing, 2.5 hours more HD video playback or 2 more hours of video recording per battery charge. ST has also opened up this technology to Globalfoundries so that they can offer it to other customers. The other way to use the technology is to maintain the same Voltage used for bulk and get a frequency boost. The tradeoff can be seen in figure 2.
Figure 2 – tradeoff between performance and power savings
But the story does not end there. The technology also supports 3D transistors or FinFETs.
Figure 3: FD SOI for 3D transistors
Here, the advantages may be even greater since the Fin for the transistors is pre-built. The Buried Oxide layer is probably about 50nm thick and the top-silicon in the order of 25-30nm, depending on the specification of the devices. With the fin created, the rest is just carved out down to the insulator. Longaria estimated that this can save up to 1 year in the development of a FinFET process.
Soitec estimates that they have the capacity to build 3M wafers a year at the moment and see demand in the range of 1.5 to 2M per year currently. It takes about 12-18 months to add additional factories. Most of the wafers being shipped today are 300mm although they have prototyped 450mm and found no show stoppers. Two other sources of these wafers are available for companies concerned about single sourcing.
For companies wanting to use this technology, there are no changes required in their existing EDA tooling, except for having new SPICE models with better characteristics than they are accustomed to.
1. C Shin et al., UCB, SOI Conference 2009 – K Cheng et al., IBM, IEDM 2009
2. FD-SOI: A process booster for ST-Ericsson’s next generation NovaThor, Part 1 http://blog.stericsson.com/blog/2012/04/st-ericsson-general/fd-soi-a-process-booster-for-st-ericssons-next-generation-novathor-part-1/Brian Bailey
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