Where does time go? Before DAC I started doing a bunch of interviews with many different companies and they are still sitting there waiting for me to take action on them. Some were taken at DAC for my emerging middle class series and several since DAC. Rest assured, they will all be resurrected and processed in time. Today, I want to go back to an interview I conducted with Kiran Vittal – Senior Director Product Marketing at Atrenta, in May. We talked about many subjects on that day, but today I want to concentrate on our discussions about power.
EDA Designline: What are the Atrenta offerings in the area of power?
Kiran: We have three main capabilities in power. It all comes under the SpyGlass power umbrella. So first and foremost, we do RTL power estimation. RTL power estimation has been around for a few years and we measure the power in RTL. You provide your libraries and the estimation testbenches to get a more accurate estimation of power, and we correlate to within 15 – 20% of silicon numbers, which is quite acceptable by most of our customers.
The second thing we do is RTL power optimization. When I say optimization, we look at different structures in your design and typically people do clock gating to reduce power. We look at your existing clock gating, and we tell you where we can improve clock gating. We use formal techniques to find new opportunities of clock gating, and then we can write out the new RTL.
The third thing we do is power verification. We start out with RTL and look at your power intent. Today people capture power intent in a UPF or a CPF file. Now you can verify if your RTL matches the power intent that you created. Basically, you can define different power islands, power domains and voltage domains and we make sure you have the right isolation logic, level shifters etc. So we tackle power across the flow – pre-synthesis, during synthesis and post-layout.
EDA Designline: Which power reductions techniques do your customers use?
Kiran: The trend we see is that the mobile guys do pretty much everything that is required to reduce power. They look at each and every aspect of their design. They do clock gating. Most of them are using our RTL power estimation product. In fact every mobile processor application chip is using SpyGlass power. What they do is to monitor power through RTL regressions. For each RTL check in, they look at the power numbers at the end of the day and they see if any particular change in RTL has increased or decreased the power. Then after two or three weeks they get a gate level netlist and they can measure the power at the gate level and from this they can recalibrate the numbers for the RTL.
In the last 2 years more networking companies have adopted our solution. What we see is these guys have not traditionally considered power. Now, suddenly they have become very concerned, possibly because of cooling costs. There is also a migration of some of these chips going into the consumer space, such as the new ARM server product that consume about one tenth of the power of previous server chips. For these kinds of designs we see more opportunities for push-button solutions, where a 20 or 25% power reduction becomes possible automatically.
EDA Designline: What was Atrenta showing at DAC this year that was new?
Kiran: In a traditional ASIC flow, a designer will often create a spreadsheet containing details about the design. These are guestimates based on early analysis, expected activity levels and experience. The ASIC vendor will take this information and does the power grid design. It relies on the fact that the power grid will be overdesigned. In one case, reported by Cisco in a paper at DAC, these early numbers were 100% off compared to silicon numbers. By bringing SpyGlass into the flow, we were able to do the estimation at RTL and track all of the relevant data, such as activity, memory access rate for each memory in the design and build the spreadsheet for them. Those numbers were within 15% of the actual silicon numbers. We showed this at the show.
We also had new capabilities in power optimization associated with the control logic of memories and see how we can reduce the power there. We are working with all of the memory vendors to make sure we can support their memories. For example, consider the case where you have a DSP and you are multiplying a number with a constant. There is no value in repetitively reading the constant, so we can help reduce these accesses. We have seen around memories, that we can often achieve a 15-20% reduction in power.
EDA Designline: What interesting trends do you see for power?
Kiran: One trend I see and we are working on is related to capturing power intent. This is not an announced product yet. Today people write UPF. In some mobile chips they have possibly 20 power domains and capture the power intent by hand. We have seen UPF files that are 80,000 lines and any small mistake can create significant problems. So we want to create a solution where the UPF is created automatically from information captured by the power architecture using a GUI based product. Then they want it to be automatically updated when design changes get made, or reconciled with those changes.
Brian Bailey – keeping you covered
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