This is a roundup of news or activities in the past few days that may be of interest to people.
The increase in size and complexity of SoC designs, along with escalating software content associated with these chips and target systems, has become a critical issue for Ricoh. To speed software development, Ricoh implemented a co-emulation methodology with the ability to combine existing register transfer level (RTL) blocks with virtual models of the design. For example, Ricoh was able to compile the RTL for its design's graphics processor unit (GPU) into a ZeBu emulator from EVE and link with minimal effort to a Synopsys Virtualizer-based virtual prototype containing system-level models of the CPU cores, buses and other logic. This approach saved the time and effort of creating models of pre-existing design blocks, accelerating the start of Ricoh's software development cycle.
Breker Verification Systems has raised $5 million in Series A funding. Funding was provided by Astor Capital Group, a private equity fund out of Far East Asia. Funds will be used as working capital to scale Breker’s operations, expanding in all areas of sales, support and research and development. Previously, Breker bootstrapped the company with a small, initial round of angel investment. That funding enabled Breker to gain market traction with TrekSoC, the first commercially available software that automates the generation of self-verifying test cases for multi-threaded system-on-chip (SoC) devices. TrekSoC is in production use at leading SoC design companies, including STMicroelectronics and NVIDIA.
Xylon has upgraded the logiCAN CAN2.0B Compatible Network Controller with new features. The logiCAN IP core now has ARM® AXI4-Lite bus interface which allows easy implementation on the latest Xilinx FPGA families, including the 7 series Artix®-7, Kintex®-7 and Virtex®-7 devices. It can be also used in Xilinx Zynq-7000 EPP devices integrating two hardened CAN peripherals when specific application requires more CAN bus controllers. The logiCAN core supports ISO11898-1 and CAN2.0B specified protocol functions. Up to 31 TX and up to 63 RX buffers ensure full back to back frame reception with low CPU overhead, even at the highest baud rates. The logiCAN is re-verified against the Robert Bosch GmbH (Bosch) C reference model.
Lattice Semiconductor has released version 2.0 of its Lattice Diamond(R) design software. Version 2.0 includes support for the new LatticeECP4(TM) FPGA family and improves the overall user experience by enabling rapid design timing closure and unveils a new, partition-based incremental design flow for LatticeECP3(TM) FPGA devices. Lattice Diamond software can be downloaded from the Lattice website at http://www.latticesemi.com/latticediamond/downloads/ for both Windows and Linux operating systems.
Microsemi Corporation says that an independent organization providing technical and scientific research, development and advisory services to national security space programs has completed reliability testing of Microsemi's commercial-grade Axcelerator® FPGAs. The tests lasted more than four years with an accumulated total of more than 26 million device-hours of testing without a single antifuse failure. Microsemi's Axcelerator FPGAs are the commercial equivalent of Microsemi's space-flight RTAX-S/SL FPGAs and share the same CMOS structures, antifuse technology, materials, processing, dimensions and programming attributes. The RTAX-S/SL FPGAs are also radiation-tolerant and include flip-flops protected against radiation-induced upsets by built-in triple-module redundancy (TMR).
Xilinx has shipped its Artix-7 Field Programmable Gate Array (FPGA) family. The new devices are targeted at applications requiring performance capabilities traditionally served by Virtex FPGAs, but the form factor of small, low-cost programmable devices, such as makers of portable medical, hand-held radio, and small cellular base.
Cadence announced that Fujitsu Semiconductor Limited adopted the Cadence Encounter Timing System for timing signoff. Fujitsu Semiconductor said that 99% of hold violations were resolved after just one iteration through the ECO flow. In addition, negligible impact was made to setup time, and better routability was achieved when compared to another vendor's signoff product. Cadence Encounter Timing System delivered comprehensive physically-aware, multi-mode, multi-corner (MMMC) analysis across the design flow, engineering change orders (ECOs), and final signoff.
Brian Bailey – keeping you covered
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