This concludes a countdown of the top ten design articles seen in the EDA Designline during my first year at the helm...
Two weeks ago, in celebration of my first year looking after the EDA Designline, I started the countdown of the top ten design articles for the week. As a reminder, these were the articles in positions 10 through 4
At 10 - Agile hardware development – nonsense or necessity?
At 9 - Power awareness in RTL design analysis
At 8 - Considerations for writing UPF for a hierarchical flow
At 7 - System-level design of mixed-signal ASICs using Simulink: Efficient transitions to EDA environments
At 6 - Energy efficient C code for ARM devices
At 5 - On-chip ESD protection for High Voltage applications in TSMC BCD technology
At 4 - ACE’ing the verification of a cache coherent system using UVM
And now, in third place for the year is an article written by Adnan Hamid of Breker Verification Systems titled “The forgotten SoC verification team”. This article targets a growing class of verification engineers who are woefully under-appreciated in terms of the complexity of the job they have to do and the lack of tools made available to them. This article defines the unique problems that SoC verification engineers face in their jobs and outlines an approach that provides a level of automation for them similar to that enjoyed by block-level verification teams.
In second place is “Designing a robust clock tree structure” written by Amol Agarwal and Priyanka Garg of Freescale Semiconductor. Clock tree robustness is a critical factor affecting SoC performance. Conventionally, engineers focus on designing a symmetrical clock tree with minimum latency and skew. However, with the current complex design needs, the authors contend that this is not enough. This article describes the factors which a designer should consider while defining clock tree architecture.
The year’s winner is:
This article has had more than double the hits of the second place paper, and yet, somewhat embarrassingly, it was not posted by me at any time within the past year. This is an article that was originally posted in 2007 and has been republished as the design article of the week because there have been some problems with the original. It is titled “Understanding Clock Domain Crossing Issues” and was written by Saurabh Verma and Ashima S. Dabare of Atrenta. Clock domain crossings (CDCs) are an integral part of any SoC. The main problems which can occur in a clock domain crossing are metastability, data loss and data incoherency. In this paper, all these issues are discussed for different types of synchronous and asynchronous clock domain crossings.
Congratulations to all of the authors and thanks for helping me make it a great year. Brian Bailey
– keeping you covered
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